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8051 - b ased mcu this document contains information on a new product under development by megawin. megawin reserves the right to change or discontinue this product without notice. ? megawin technology co., ltd. 200 5 all right s reserved. 20 1 5 / 11 version 1 . 03 mg82fg5b32 / mg82fg5b16 / mg82fg5b 08 data sheet version: 1 . 03
2 mg82fg5b xx data sheet megawin
megawin mg82fg5b xx data sheet 3 features ? 1 - t 80c51 central processing unit ? mg82fg5b32/mg82fg5b16 /mg82fg5b08 with 32 k /16k/ 8 k byte s flash rom isp memory zone could be optioned as 1kb/1.5k b ~ 4 kb flexible iap size by software configured c ode protection for flash memory access flash erase/program cycle: 10,000 times flash data retention: 100 years at 25 default mg82fg5b32 flash space mapping ? ap flash default mapping ( 2 9.5 kb, 0000h~ 75 ffh ) ? iap flash default mapping ( 1 kb, 7 6 00h~ 7 9ffh ) ? isp flash default mapping (1.5kb, 7 a00h~ 7 fffh ), isp boot code default mg82fg5b 16 flash space mapping ? ap flash default mappi ng ( 13.5 kb, 0000h~ 35 ffh ) ? iap flash default mapping ( 1 kb, 36 00h~ 3 9ffh ) ? isp flash default mapping (1.5kb, 3 a00h~ 3 fffh ), isp boot code default mg82fg5b 08 flash space mapping ? ap flash default mapping ( 5 .5 kb, 0000h~ 1 5 ffh ) ? iap flash default mapping ( 1 kb, 1 6 00h~ 1 9ffh ) ? isp flash default mapping (1.5kb, 1 a00h~ 1 fffh ), isp boot code ? data ram on - chip 256 byte s scratch - pad ram mg82fg5b32 - 1792 bytes expanded ram (xram) mg82fg5b 16 - 768 bytes expanded ram (xram) mg82fg5b08 - 256 bytes expanded ram (xram) ? dual data point er ? interrupt controller 16 sources, f our - level - priority interrupt capability four external interrupt inputs , nint0, nint1, nint2 and nint3 , with glitch filter all external interrupts support high/low level or rising/falling edge trigger ? three 16- bit timer/ counter s, timer 0, timer 1 and timer 2 t0cko on p34, t1cko on p35 and t2cko on p10 x12 mode enabled for t0/t1/t2 s1brg cascaded with timer 1 to a 16/24 - bit timer/counter ? programmable 16- bit c ounter /timer array (pca ) with 8 compare/capture m odules programma ble 16 - bit pca base counter u p to 100 mhz clock source from on- chip ckm capture mode , 16- bit software timer mode and high speed output mode 8/10/12/16 - bit pwm mode with phase shift function , up to 8 - channel pwm pwm module with dead - time control and central - aligned option ? keypad interrupt ? 1 0 - b it adc programmable throughput up to 2 0 0 ksps up to 8 channel single - ended inputs ? enhanced uart (s0) fram ing error detection automatic address recognition speed improvement mechanis m (x2/x4 mode) spi master supported in mode 4 ? secondary uart (s1)
4 mg82fg5b xx data sheet megawin dedicated baud rate generator shares to s0 or set as an 8 - bit timer spi master supported in mode 4 ? one master/slave spi serial i nterface (spi) max. spi clock frequency up to 12mhz. up to 3 spi master s including s0 and s1 in mode 4 ? three two - wire - interface : twi 0 , twi1 and s twi (sid ) two master/slave hardware engine : twi 0 and twi1 3 device address recognized in twi 0 /twi1 slave mode two wire i nterface start/stop detection (sid) to support software twi slave (stwi) ? on - chip - debug interf ace (ocd) ? programmable watch d og timer , clock sourced from ilrco one time enabled by cpu or power - on interrupt cpu or reset cpu on wdt overflow support wdt function in power down mode (watch mode) ? real - time - clock module 0.5s ~ 64s programmable interrupt per iod 21- bit length system timer ? beeper fun c tion ? maximum 29 gpios in 32- pin package p3 can be configured to quasi - bidirectional, push - pull output, open - drain output and input only p1, p2, p4 and p6 can be configured to open - drain output or push - pull output p 6.0 , p6.1 and p4.7 shared with xtal2 , xt al1 and rst ? multiple p ower control modes : idle mode , power - down mode , slow mode, sub - clock mode, rtc mode, watch mode and monitor mode. all interrupt s can wake up idle mode 11 sources to wake up power - down mode slow mode and sub - clock mode support low speed mcu operation rtc mode supports rtc to resume cpu in power down w atch mode supports wdt to resume cpu in power down monitor mode supports bod1 to resume cpu in power down ? two brown - out detector s bod0: detect 1 . 7 v b od1: selected detection level on 4.2v/3.7v/2.4v/2.0v i nterrupt cpu or reset cpu wake up cpu in power - down mode ? o peratin g voltage range: 1 . 8 v ? 5.5v minimum 1 . 7 v requirement in flash write operation (isp/iap/icp) ? operatin g frequency range : 25 mhz(max) extern al crystal mode, 0 ? 12mhz @ 1 . 8 v ? 5.5v and 0 ? 25mhz @ 2. 7 v ? 5.5v cpu up to 12mhz @ 1 . 8 v ? 5.5v and up to 25mhz @ 2. 2 v ? 5.5v ? clock sources internal 1 2mhz/1 1.059 mhz oscillator (ihrco): factory calibrated to r 1%, typical external crystal mode , support 32 .768khz oscillating and missing clock detection (mcd) internal low power 32khz rc oscillator (ilrco) external clock input (ecki) on p6.0/xtal2 internal oscillator output on p6.0/xtal2 on - chip clock multiplier (ckm) to provide high speed clock source ? operat ing temperature: industrial ( - 40 c to + 8 5 c )* ? 1 6 - b y t es unique id code ? package types: lqfp 32 (7mm x 7mm): mg82fg5b32 ad 32 , mg82fg5b 16 ad 32 so p2 8 : mg 82f g5b 32 a s28 , mg 82f g5b 16 a s28
megawin mg82fg5b xx data sheet 5 so p2 0 : mg 82f g5b 32 a s20 , mg 82f g5b 16 a s20 , mg82fg5b08as 2 0 s so p 16 : mg82fg5b08a l 16 * : tested by sampling.
6 mg82fg5b xx data sheet megawin content features ............................................................................................................. 3 content .............................................................................................................. 6 1. general descr iption ..................................................................................... 11 2. ordering information .................................................................................... 12 3. block diagram ............................................................................................. 13 4. spec ial function register ............................................................................ 14 4.1. sfr map (page 0~f) ................................................................ ................................... 14 4.2. sfr bit assignment (page 0~f) ................................................................ ................... 16 4.3. auxiliary sfr map (page p) ................................................................ ......................... 19 4.4. auxiliary sfr bit assignment (page p) ................................................................ ........ 20 5. pin configurations ....................................................................................... 21 5.1. package instruction ................................ ................................ ...................................... 21 5.2. pin description ................................ ................................ ................................ ............. 23 5.3. alt ernate function redirection ................................ ................................ ...................... 25 6. 8051 cpu function description ................................................................... 28 6.1. cpu register ................................................................ ............................................... 28 6.2. cpu timing ................................................................ .................................................. 29 6.3. cpu addressing mode ................................................................ ................................. 30 7. memory organization .................................................................................. 31 7.1. on - chip program flash ................................................................ ................................ 31 7.2. on - chip data ram ................................................................ ....................................... 32 7.3. on - chip expanded ram (xram) ................................................................ .................. 34 7.4. declaration identifiers in a c51 - compiler ................................................................ ..... 35 8. dual data pointer register (dptr) ............................................................. 36 9. system clock ............................................................................................... 37 9.1. clock structure ................................ ................................ ................................ ............. 38 9.2. clock register ................................................................ .............................................. 39 9.3. system clock sample code ................................................................ ......................... 42 10. watch dog timer (wdt) ............................................................................. 43 10.1. wdt structure ................................................................ .............................................. 43 10.2. wdt during idle and power down ................................................................ ............... 43 10.3. wdt register ................................................................ ............................................... 44 10.4. wdt hardware op tion ................................................................ ................................. 45 10.5. wdt sample code ................................................................ ....................................... 46 11. real - time - clock(rtc)/system - timer ......................................................... 48 11.1. rtc structure ................................................................ .............................................. 48 11.2. rtc register ................................................................ ................................................ 49 11.3. rtc sample code ................................................................ ....................................... 51 12. system reset .............................................................................................. 53 12.1. reset source ................................................................ ................................................ 53 12.2. power - on reset ................................................................ ........................................... 53 12.3. external reset ................................................................ .............................................. 54 12.4. software reset ................................ ................................ ................................ ............. 54 12.5. brown - out reset ................................................................ .......................................... 55 12.6. wdt reset ................................................................ ................................................... 55 12.7. illegal address reset ................................ ................................ .................................... 55 12.8. reset sample code ................................ ................................ ..................................... 56 13. power management ..................................................................................... 57 13.1. brown - out detector ................................ ................................ ...................................... 57 13.2. power saving mode ................................ ................................ ..................................... 58
megawin mg82fg5b xx data sheet 7 13.2.1. slow mode ............................................................................................................................ 58 13.2.2. sub - clock mode ................................................................................................................... 58 13.2.3. rtc mode ............................................................................................................................. 58 13.2.4. watch mode .......................................................................................................................... 58 13.2.5. monitor mode ........................................................................................................................ 58 13.2.6. idle mode .............................................................................................................................. 58 13.2.7. power - down mode ................................................................................................................ 58 13.2.8. interrupt recovery from power - down ................................................................................... 60 13.2.9. reset recovery from power - down ....................................................................................... 60 13.2.10. kbi wakeup recovery from power - down ..................................................................... 60 13.3. power control register ................................................................ ................................. 61 13.4. power control sample code ................................................................ ........................ 63 14. configurable i/o ports ................................................................................. 66 14.1. io structure ................................................................ .................................................. 66 14.1.1. port 3 quasi - bidirectional io structure ................................................................................. 66 14.1.2. port 3 push - pull output structure ........................................................................................ 67 14.1.3. port 3 input - only (high impedance input) structure ............................................................ 67 14.1.4. port 3 open - drain output structure ..................................................................................... 67 14.1.5. general open - drain output structure .................................................................................. 68 14.1.6. general push - pull output structure ..................................................................................... 68 14.1.7. general port input configured .............................................................................................. 69 14.2. i/o port register ................................................................ ........................................... 70 14.2.1. port 1 register ...................................................................................................................... 70 14.2.2. port 2 register ...................................................................................................................... 71 14.2.3. port 3 register ...................................................................................................................... 71 14.2.4. port 4 register ...................................................................................................................... 71 14.2.5. port 6 register ...................................................................................................................... 72 14.2.6. pull - up control register ....................................................................................................... 72 14.3. gpio port s ample code ................................ ................................ .............................. 74 15. interrupt ....................................................................................................... 75 15.1. interrupt structure ................................................................ ......................................... 75 15.2 . interrupt source ................................................................ ............................................ 77 15.3. interrupt enable ................................................................ ............................................ 78 15.4. interrupt priority ................................................................ ............................................ 79 15.5. interrupt process ................................................................ .......................................... 79 15.6. ninti input source selection and input filter (i=0~3) ................................................... 80 15.7. interrupt register ................................................................ .......................................... 81 15.8. interrupt sample code ................................................................ .................................. 88 16. timers/counters .......................................................................................... 89 16.1. ti mer 0 and timer 1 ................................ ................................ ..................................... 90 16.1.1. timer 0/1 mode 0 .................................................................................................................. 90 16.1.2. timer 0/1 mode 1 .................................................................................................................. 91 16.1.3. timer 0/1 mode 2 .................................................................................................................. 92 16.1.4. timer 0/1 mode 3 .................................................................................................................. 93 16.1.5. timer 0/1 programmable clock - out ..................................................................................... 94 16.1.6. timer 0/1 register ................................................................................................................ 96 16.2. timer 2 ................................................................ ......................................................... 98 16.2.1. capture mode (cp) ............................................................................................................... 98 16.2.2. auto - reload mode (ar) ........................................................................................................ 99 16.2.3. baud - rate generator mode (brg) .................................................................................... 101 16.2.4. timer 2 programmable clock output ................................................................................. 102 16.2.5. timer 2 register ................................................................................................................. 103 16.3. timer sample code ................................ ................................ .................................... 106 17. serial port 0 (uart0) ................................................................................ 109 17.1. serial port 0 mode 0 ................................ ................................ ................................... 110 17.2. serial port 0 mode 1 ................................ ................................ ................................... 112 17.3. serial port 0 mode 2 and mode 3 ................................................................ ............... 113 17.4. frame error detection ................................................................ ................................ 113
8 mg82fg5b xx data sheet megawin 17.5. multiprocessor communications ................................................................ ................. 114 17.6. automatic address recognition ................................................................ .................. 114 17.7. baud rate setting ................................................................ ...................................... 116 17.7.1. baud rate in mode 0 .......................................................................................................... 116 17.7.2. baud rate in mode 2 .......................................................................................................... 116 17.7.3. baud rate in mode 1 & 3 .................................................................................................... 116 17.8. serial port 0 mode 4 (spi master) ................................................................ .............. 124 17.9. serial port 0 register ................................................................ ................................. 126 18. serial port 1 (uart1) ................................................................................ 129 18.1. serial port 1 baud rate generator (s1brg) ................................ .............................. 129 18.2. serial port 1 baud rate setting ................................................................ .................. 130 18.2.1. baud rate in mode 0 .......................................................................................................... 130 18.2.2. baud rate in mode 2 .......................................................................................................... 130 18.2.3. baud rate in mode 1 & 3 .................................................................................................... 130 18.3. serial port 1 mode 4 (spi master) ................................................................ .............. 132 1 8.4. pure timer mode of s1brg ................................................................ ....................... 134 18.5. s1brt programmable clock output ................................................................ .......... 135 18.6. s1 baud rate generator (s1brg) for s0 ................................................................ ... 136 18.7. serial port 1 register ................................................................ ................................. 137 18.8. serial port sample code ................................ ................................ ............................ 140 19. programmable counter array (pca) ......................................................... 141 19.1. pca overview ................................................................ ............................................ 141 19.2. pca timer/counter ................................ ................................ .................................... 142 19.3. compare/capture modules ................................................................ ......................... 144 19.4. operation modes of the pca ................................................................ ...................... 147 19.4.1. capture mode ..................................................................................................................... 147 19.4.2. 16- bit software timer mode ................................................................................................ 148 19.4.3. high speed output mode ................................................................................................... 149 19.4.4. pwm mode ......................................................................................................................... 150 19.4.5. enhance pwm mode .......................................................................................................... 151 19.5. pca sample code ................................................................ ..................................... 159 20. serial peripheral interface (spi) ................................................................ 160 20.1. typical spi configurations ................................................................ ......................... 161 20.1.1. single master & single s lave .............................................................................................. 161 20.1.2. dual device, where either can be a master or a slave ...................................................... 161 20.1.3. single master & multiple slaves ......................................................................................... 161 20.2. configuring the spi ................................ ................................ .................................... 162 20.2.1. additional considerations for a slave ................................................................................. 162 20.2.2. additional considerations for a master ............................................................................... 162 20.2.3. mode change on nss - pin ................................................................................................... 163 20.2.4. transmit holding register fu ll flag ................................................................................... 163 20.2.5. write collision ..................................................................................................................... 163 20.2.6. spi clock rate select ......................................................................................................... 163 20.3. data mode ................................ ................................ ................................ .................. 164 20.4. spi register ................................................................ ............................................... 166 20.5. spi sample code ................................................................ ....................................... 168 21. two wire serial interface (twi0 and twi1) ............................................... 169 21.1. operating modes ................................................................ ........................................ 170 21.1.1. master transmitter mode .................................................................................................... 170 21.1.2. master receiver mode ........................................................................................................ 170 21.1.3. slave transmitter mode ...................................................................................................... 171 21.1.4. slave receiver mode .......................................................................................................... 171 21.2. miscellaneous states ................................ ................................ .................................. 172 21.3. using the twi0 ................................ ................................ ................................ ........... 172 21.4. twi0 register ................................................................ ............................................ 178 21.5. twi1 register ................................................................ ............................................ 181 21.6. twi 0 sample code ................................ ................................ .................................... 184
megawin mg82fg5b xx data sheet 9 22. serial interface detection (sid/stwi) ........................................................ 186 22.1. sid structure ................................................................ .............................................. 186 22.2. sid register ................................................................ ............................................... 187 22.3. sid sample code ................................................................ ....................................... 188 23. beeper ....................................................................................................... 209 23.1. beeper registe r ................................................................ .......................................... 209 23.2. beeper sample code ................................................................ ................................. 210 24. keypad interrupt (kbi) ............................................................................... 211 24.1. keypad register ................................................................ ......................................... 211 24.2. keypad interrupt sample code ................................ ................................ ................... 213 25. 10 - bit adc ................................................................................................. 214 25.1. adc structure ................................................................ ............................................ 214 25.2. adc operation ................................ ................................ ................................ ........... 215 25.2.1. adc input channels ........................................................................................................... 215 25.2.2. starting a conversion ......................................................................................................... 215 25.2.3. adc conversion time ........................................................................................................ 215 25.2.4. i/o pins used wit h adc function ....................................................................................... 215 25.2.5. idle and power - down mode ................................................................................................ 216 25.3. adc register ................................................................ ............................................. 217 25.4. adc sample code ................................................................ ..................................... 221 26. isp and iap ............................................................................................... 222 26.1. mg82fg5b32 flash memory configuration ............................................................... 222 26.2. mg82fg5bxx flash access in isp/iap ................................ ................................ .... 223 26.2.1. isp/iap flash page erase mode ........................................................................................ 224 26.2.2. isp/iap flash program mode ............................................................................................. 226 26.2.3. isp/iap flash read mode .................................................................................................. 228 26.3. isp operation ................................................................ ............................................. 230 26.3.1. hardware approached isp .................................................................................................. 230 26.3.2. software approached isp ................................................................................................... 230 26.3.3. notes for isp ....................................................................................................................... 231 26.4. iap operation ................................................................ ............................................. 232 26.4.1. iap - memory boundary/range ............................................................................................ 232 26.4.2. update data in iap - memory ................................................................................................ 232 26.4.3. notes for iap ....................................................................................................................... 233 26.5. isp/iap register ................................................................ ......................................... 234 26.6. sample code for isp ................................ ................................ ................................... 237 27. page p sfr access .................................................................................. 238 27.1. page p sfr access sample code ................................................................ ............. 242 28. auxiliary sfrs ........................................................................................... 244 29. hardware option ........................................................................................ 248 30. application notes ....................................................................................... 250 30.1. power supply circuit ................................ ................................ .................................. 250 30.2. reset circuit ................................................................ ............................................... 250 30.3. xtal oscillating circuit ................................................................ .............................. 251 30.4. icp and ocd interface circuit ................................ ................................ .................... 252 30.5. in - chip - programming function ................................ ................................ ................... 253 30.6. on - chip - debug function ................................ ................................ ............................ 254 30.7. sample code for unique id read ................................................................ ................. 255 31 . electrical characteristics ............................................................................ 256 31.1. absolute maximum rating ................................ ................................ .......................... 256 31.2. dc characteristics ................................................................ ...................................... 257 31.3. external clock characteristics ................................ ................................ .................... 259 31.4. ihrco characteristics ................................................................ ............................... 259 31.5. ilrco characteris tics ................................................................ ................................ 259 31.6. ckm characteristics ................................ ................................ ................................... 260
10 mg82fg5b xx data sheet megawin 31.7. flash characteristics ................................ ................................ .................................. 260 31.8. adc characteristics ................................ ................................ ................................... 261 31.9. serial port timing characteristics ................................................................ ............... 262 31.10. spi timing characteristics ................................................................ ......................... 263 32. instruction set ............................................................................................ 265 33. package dimension ................................................................................... 268 33.1. lqfp - 32 (7mm x 7 mm) ................................ ................................ ............................. 268 33.2. sop - 28 ................................................................ ...................................................... 269 33.3. sop - 20 ................................................................ ...................................................... 270 33.4. ssop - 16 ................................................................ .................................................... 271 34. revision history ......................................................................................... 272
megawin mg82fg5b xx data sheet 11 1. general description the mg82fg5b xx is a single - chip microcontroller based on a high performance 1 - t architecture 80c51 cpu that execu tes instructions in 1~7 clock cycles (about 6~7 times the rate of a standard 8051 device), and has an 8051 compatible instruction set. therefore at the same performance as the standard 8051, the mg82fg5bxx can operate at a much lower speed and thereby grea tly reduce the power consumption. the mg82fg5bxx has 32 k /16k /8k bytes of embedded flash memory for code and data. the flash memory can be programmed either in serial writer mode (via icp, in - circuit programming) or in in - system programming mode . and, it a lso provides the in - application programming (iap) capability. icp and isp allow the user to download new code without removing the microcontroller from the actual end product; iap means that the device can write non - volatile data in the flash memory while the application program is running. there needs no external high voltage for programming due to its built - in charge - pumping circuitry. the mg82fg5bxx retains all features of the standard 80c52 with 256 bytes of scratch - pad ram, three 8 - bit i/o ports, two external interrupts, a multi - source 4 - level interrupt controller, a serial port (uart0) and three timer/counters. in addition, the mg82fg5bxx has t hree extra i/o port pin s (p4 .5 , p4.4, p4.1, p4.0, p 6.1 and p6 .0 ), mg82fg5bxx one xram of 1 792 /768 bytes, two extra external interrupts with high/low trigger option, 10- bit a dc, a 8 - channel pca with dead - time controlled pwm , one spi, two twi s (twi 0 and twi1) , secondary serial port (uart1), keypad interrupt, watchdog timer, real - time - clock module , two brown - out det ectors, an on- chip crystal oscillator(shared with p6.0 and p6.1 ), an internal high precision oscillator (ihrco) , an on - chip clock multiplier (ckm) to generate high speed clock source, an internal low speed rc oscillator (ilrco) and an enhanced serial funct ion in uart0 that facilitates multiprocessor communication and a speed improvement mechanism (x2/x4 mode). the mg82fg5bxx has multiple operating modes to reduce the power consumption: idle mode, power down mode, slow mode, sub - clock mode, rtc mode, watch mode and monitor mode. in the idle mode the cpu is frozen while the peripherals and the interrupt system are still operating. in the power - down mode the ram and sfrs? value are saved and all other functions are inoperative; most importantly, in the power - d own mode the device can be waked up by many interrupt or reset source s . in slow mode , the user can further reduce the power consumption by using the 8 - bit system clock pre - scal e r to slow down the operating speed. o r select sub - clock mode which clock source is derived from internal low speed oscillator (ilrco) for cpu to perform an ultra low speed operation. the rtc module supports real - time - clock unction in all modes. in watch mode, it keeps wdt running in power - down or idle mode and resumes cpu when wdt ov erflows. monitor mode provides the brown - out detection in power down mode and resumes cpu when chip vdd reaches the specific detection level. additionally, the mg82fg5bxx is equipped with the megawin proprietary on - chip debug (ocd) interface for in - circui t emulator (ice). the ocd interface provides on - chip and in - system non - intrusive debugging without any target resource occupied. several operations necessary for an ice are supported such as reset, run, stop, step, run to cursor and breakpoint setting. the user has no need to prepare any development board during firmware developing or the socket adapter used in the traditional ice probe head. all the thing the user needs to do is to prepare a connector for the dedicated ocd interface. this powerful feature make s the developing very easy for any user.
12 mg82fg5b xx data sheet megawin 2. ordering information figure 2 ? 1 . ordering information mg 82 f g 5 xx yy zz megawin device family 82 = high - performance 1 t 8051 core 87 = stand 12t / 6t 8051 core with internal osc 84 = high-performance 1t 8051 core with usb interface program memory type f = flash o = otp c = rom operating voltage range g = 1.8v ? 5.5v l = 2.4v ? 3.6v e = 4.5v ? 5.5v pin count 32 = 32 pins 28 = 28 pins 20 = 20 pins package type ad = lqfp ay = qfn program memory size 32 = 32 kbyte 16 = 16 kbyte 08 = 08 kbyte device sub family 5 = periphery with adc series 3 = high pin count with pure i/o series 1 = low pin count with pure i/o series 89 = stand 12t / 6t 8051 core as = sop al = ssop
megawin mg82fg5b xx data sheet 13 3. block diagram figure 3 ? 1 . block diagram 8051 cpu (1t) xtal osc clock multiplier wdt ram 256 x 8 xram 1792 x 8 flash 32k x 8 uart0 timer0 timer1 timer2 pca pwm x 8 port1 port2 port3 port4 ext. int bod0 bod1 (p3.2) nint0 (p3.3) nint1 (p4.4) nint2 (p4.5) nint3 (p3.4) t0/t0cko (p3.5) t1/t1cko (p1.0) t2/t2cko (p3.0) rxd0 (p3.1) txd0 (p4.7) rst p1.0~p1.7 p2.0~p2.7 p3.0~p3.5 p4.0, p4.1, p4.4, p4.5, p4.7 (p6.1) xtal1 (p6.0) icko/ecki/xtal2 (p1.1) t2ex (p2.1) eci isp/iap 10-bit adc uart1 (lin/smc) (p1.2) rxd1 (p1.3) txd1 (p2.2~p2.7) cex0~cex5 (p2.0~p2.1) pwm6~pwm7 (p1.0~p1.7) ain0~ain7 kbi (p2.0~p2.7) kbi0~kbi7 ocd_scl ocd_sda ocd interface spi (p1.4) nss (p1.5) mosi (p1.6) miso (p1.7) spiclk vdd twi0 (3 slave addr) (p4.0) twi0_scl (p4.1) twi0_sda ihrco 12mhz/ 11.059m ilrco 32khz port6 p6.0~p6.1 rtc twi1 (3 slave addr) (p1.0) twi1_scl (p1.1) twi1_sda stwi sta/sto detection (sid) (nint1) stwi_scl (s0mi) stwi_sda
14 mg82fg5b xx data sheet megawin 4. special function register 4.1. sfr map (page 0~f) table 4 ? 1 . sfr map (page 0~f) page index 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8 0 * p 6 ch ccap0h * ccap1h * ccap2h * ccap3h * ccap4h * ccap5h * 1 * ccap6h * ccap 7 h * -- -- -- -- f0 0 * b paoe pcapwm0 * pcapwm1 * pcapwm2 * pcapwm3 * pcapwm4 * pcapwm5 * 1 * pcapwm6 * pcapwm7 * -- -- -- -- e8 0 * p4 cl ccap0l * ccap1l * ccap2l * ccap3l * ccap4l * ccap5l * 1 * ccap6l * ccap 7 l * -- -- -- -- e0 0 1 acc wdtcr ifd ifad rh ifadrl ifmt scmd ispcr d8 0 * ccon cmod ccapm0 * ccapm1 * ccapm2 * ccapm3 * ccapm4 * ccapm5 * 1 * ccapm7 * ccapm7 * -- -- -- -- d0 0 * psw siadr * sidat * sista * sicon * kbpatn kbcon kbmask 1 * si 1 adr * si 1 dat * si 1 sta * si 1 con * c8 0 1 t2con t2mod rcap2l rca p2h tl2 th2 clrl chrl c0 0 1 xicon xicfg -- adcfg0 adcon0 adcdl adcdh ckcon0 b8 0 1 ip0l saden -- adcfg1 pwmcr pdtcr rt c cr ckcon1 b0 0 * p3 p3m0 p3m1 p4m0 pucon0 * -- rtctm ip0h 1 * pucon1 * p 6 m0 * a8 0 1 ie saddr -- -- sfrpi * eie1 eip1l eip1h a0 0 1 p2 auxr0 auxr1 auxr2 auxr3 -- -- -- 98 0 * s0con * s0buf * -- -- s0cfg * -- -- -- 1 * s1con * s1buf * s1brt * s1brc * s1cfg * -- * 2 * 90 0 1 p1 p1m0 p1aio -- -- p2m0 borev pcon1 88 0 1 tcon tmod tl0 tl1 th0 th1 sfie -- 80 0 1 -- sp dpl dph spstat s p con spdat pcon0 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f *: user needs to set sfr pi as sfrpi=0x00 ~ 0x0 2 for sfr page access. sfrpi: sfr page index register sfr page = 0~f sfr address = 0xac reset = xx xx- 0000 7 6 5 4 3 2 1 0 -- -- -- -- pidx3 pidx2 pidx1 pidx0 w w w w r/w r/w r/w r/w bit 7 ~4: reserved. software must write ? 0 ? on these bits when sfrpi is written. bit 3~0: sfr page index. the available pages are only page ? 0 ? and ? 1 ? . pidx [ 3 :0] selected page 0000 page 0 0001 page 1 0010 page 2
megawin mg82fg5b xx data sheet 15 0011 page 3 ?? ?? ?? ?? ?? ?? 1111 page f
16 mg82fg5b xx data sheet megawin 4.2. sfr bit assignment (page 0~f) table 4 ? 2 . sfr bit assignment (page 0~f) symbol description addr bit address and symbol reset v alue bit - 7 bit - 6 bit - 5 bit - 4 bit - 3 bit - 2 bit - 1 bit - 0 sp sta ck pointer 81h 00000111 dpl data pointer low 82h 00000000 dph data pointer high 83h 00000000 spstat spi status register 84h spif wcol thrf spibsy modf -- -- spr2 0000 0xx 0 spcon spi control register 85h ssig spen dord mstr cpol c pha spr1 spr0 00000 1 00 spdat spi data register 86h spdat.7 spdat.6 spdat.5 spdat.4 spdat.3 spdat.2 spdat.1 spdat.0 00000000 pcon 0 power control 0 87h smod 1 smod0 gf pof 0 gf1 gf0 pd idl 00010000 tcon timer control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 0000 0000 tmod timer mode 89h gate c/t m1 m0 gate c/t m1 m0 00000000 tl0 timer low 0 8ah 00000000 tl1 timer low 1 8bh 00000000 th0 timer high 0 8ch 00000000 th1 timer high 1 8dh 00000000 sfie system flag int en. 8eh sidfie mcdre mcdfie rtcfie -- bof1ie bof0ie wdtfie xxxxx 000 p1 port 1 90h p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 11111111 p1m0 p1 mode register 0 9 1 h p1m0.7 p1m0.6 p1m0.5 p1m0.4 p1m0.3 p1m0.2 p1m0.1 p1m0.0 0 0 000000 p1 aio p1 analog input only 92h p17 aio p16 aio p15 aio p14 aio p13 aio p12 aio p11 aio p10 aio 0 0 000000 p2m0 p2 mode register 0 9 5 h p2m0.7 p2m0.6 p2m0.5 p2m0.4 p2m0.3 p2m0.2 p2m0.1 p2m0.0 0 0 000000 borev bit order reversed 96h 0 0 000000 pcon1 power control 1 97h swrf exrf mcdf rtcf -- bof1 bof0 wdt f 00 0 0 x 000 s 0 con serial 0 control 98h sm00 /fe sm10 sm20 ren0 tb80 rb80 ti0 ri0 00000000 s 1 con serial 1 control 98h sm01 sm11 sm21 ren1 tb81 rb81 ti1 ri1 00000000 ---- ---- 98h -- -- -- -- -- -- -- -- ---- s 0 buf serial 0 buffer 99h xxxxxxxx s1 buf serial 1 buffer 99h xxxxxxxx ---- ---- 9 9 h -- -- -- -- -- -- -- -- ---- ---- ---- 9ah -- -- -- -- -- -- -- -- ---- s1brt s1 baud - rate timer 9ah 00000000 ---- ---- 9 a h -- -- -- -- -- -- -- -- ---- ---- ---- 9 b h -- -- -- -- -- -- -- -- ---- s1brc s1 baud - rate counter 9bh 00000000 ---- ---- 9 b h -- -- -- -- -- -- -- -- ---- s0cfg s0 configuration 9ch urts smod2 urm0x3 sm30 s0dor bti utie -- 0000100x s1cfg s1 configuration 9ch sm31 s1 evps s1dor s1tr s1mod1 s1tx12 s1ckoe s1tme 00100000 ---- ---- 9 c h -- -- -- -- -- -- -- -- ---- ---- ---- 9dh -- -- -- -- -- -- -- -- ---- ---- ---- 9dh -- -- -- -- -- -- -- -- ---- ---- ---- 9dh -- -- -- -- -- -- -- -- ---- p2 port 2 a0h p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 11111111 auxr 0 auxiliary register 0 a1 h p60oc1 p60oc0 p60fd t0xl p4fs1 p4fs0 int1h int0h 000 0 00 00 auxr1 auxiliary register 1 a2h p1kbih p3kbil p4spi p3s1 p3s1mi p6twi 0 p3cex dps 0 0000000 auxr2 auxiliary register 2 a3h int3is1 int3is0 int2is1 int2is0 t1x12 t0x12 t1ckoe t0ckoe 00000000 auxr3 auxiliary register 3 a4h staf stof bpoc1 bpoc0 gf p1s0mi p3eci p3twi1 000 0 00 00 ie interrupt enable a8h ea gf4 et2 es 0 et1 ex1 et0 ex0 0 00 00000 saddr slave address a9h 00000000 sfrpi sfr page index ach -- -- -- -- idx3 idx 2 idx1 idx0 xxxx 0000 eie1 extended int enable 1 adh etwi1 etwi 0 ekb es1 esf epca eadc espi 0 0000000 eip1l ext. int priority 1 low aeh ptwi1l ptwi 0 l pkbl ps1l psfl ppcal padcl pspil 0 0000000 eip1h ext. int priority 1 high afh ptwi1h ptwi 0 h pkbh p s1 h psfh ppcah padch pspih 0 0000000 p3 port 3 b0h -- -- p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 xx 111111 p 3 m0 p3 mode register 0 b 1 h -- -- p3 m0.5 p3 m0.4 p3 m0.3 p3 m0.2 p3 m0.1 p3 m0.0 0 0 000000 p3 m1 p3 mode register 1 b 2h -- -- p3 m1.5 p3 m1.4 p3 m1.3 p3 m1.2 p3 m1.1 p3 m1.0 0 0 000 000 p4 m0 p4 mode register 0 b 3 h p4m0.7 -- p4 m0.5 p4 m0.4 -- -- p4 m0.1 p4 m0.0 0 x 00 xx00 pucon0 port pull - up control 0 b4h p4pu1 p4pu0 p2pu1 p2pu0 p1pu1 p1pu0 -- -- 000000xx pucon1 port pull - up control 1 b4h -- -- -- -- -- p6pu0 -- -- xxxxx0xx ---- ---- b5 h -- -- -- -- -- -- -- -- ---- p6m0 p6 mode register 0 b5h -- -- -- -- -- -- p6m0.1 p6m0.0 xxxxxx 00 ip 0 h interrupt priority 0 high b7h px3h px2h pt2h p sh pt1h px1h pt0h px0h 000 00000 ip 0 l interrupt priority low b8h px3l px2l pt2l psl pt1l px1l pt0l px0l 000 00000 saden slave address mask b9h 00000000 adcfg1 adc configuration 1 bbh -- vrs2 vrs1 sign aos.3 aos.2 aos.1 aos.0 x 0000000 pwmcr pwm control bch pcae exdt -- pfcf pfcm pfcs2 pfcs1 pfcs0 00x0000 0
megawin mg82fg5b xx data sheet 17 pdtcr pwm dead - time control bdh dtps1 dtps 0 dt.5 dt.4 dt.3 dt.2 dt.1 dt.0 00000000 rtccr rtc control register beh rtce rtco rtcrl5 rtcrl4 rtcrl3 rtcrl2 rtcrl1 rtcrl0 00111111 ckcon1 clock control 1 bfh -- -- xcks5 xcks4 xcks3 xcks2 xcks1 xcks0 xx000000 x icon ext ernal i nt control c0h i n t3h ex3 i e 3 it3 i n t2h ex2 ie 2 it2 0000 0000 xicfg ext. int. configured c1h int1is1 int 1 is0 int 0 is1 int 0 is0 x3flt x2flt x1flt x0flt 00000000 adcfg0 adc configuration 0 c3h adcks2 adcks1 adcks0 adrj adps vrs0 adtm1 adtm0 0000 00 00 adcon0 adc control 0 c4h adcen -- c h3 adci adcs chs2 chs1 chs0 0 x 000000 adcdl adc data low c5h adcv.1 adcv.0 -- -- -- -- -- -- 00 xxxxxx adcdh adc data high c6h adcv.9 adcv.8 adcv.7 adcv.6 adcv.5 adcv.4 adcv.3 adcv.2 00000000 ckcon0 clock control 0 c7h afs enckm ckmis1 ckmis0 ccks sck s 2 s ck s 1 scks0 0 001 0 000 t2con timer 2 control c8h tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl 2 00000000 t2mod timer2 mode c9h - - - - t2exh t2x12 - - - - t2oe dcen 2 xx 00 xx 00 rcap2l timer2 capture low cah 00000000 rcap2h timer2 capture high cbh 0000 0000 tl2 timer low 2 cch 00000000 th2 timer high 2 cdh 00000000 clrl cl reload register ceh 00000000 chrl ch reload register cfh 00000000 psw program status word d0h cy ac f0 rs1 rs0 ov f1 p 00000000 siadr twi 0 address reg. d1h gc 00000000 si 1 adr twi 1 address reg. d1h gc 1 00000000 sidat twi 0 data reg. d2h 00000000 si 1 dat twi 1 data reg. d2h 00000000 sista twi 0 status reg. d3h 11111000 sis 1 ta twi 1 status reg. d3h 11111000 sicon twi 0 control reg. d4h cr2 ensi sta sto s i aa cr1 cr0 00000000 si 1 con twi 1 control reg. d4h cr2 1 ensi 1 sta 1 sto 1 s i 1 aa 1 cr1 1 cr0 1 00000000 kbpatn keypad pattern d5h 11111111 kbcon keypad control d6h -- -- -- -- -- -- patns kbif xxxxxx01 kbmask keypad int. mask d7h 00000000 ccon p c a control reg. d8h cf cr ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 00000000 cmod pca mode reg. d9h cidl bme4 bme2 bme0 cps2 cps1 cps0 ecf 0 0000 000 ccapm0 pca module0 mode dah dte0 ecom0 capp0 capn0 mat0 tog0 pwm0 eccf0 0 0000000 ccapm6 pca module6 mode dah bme6 pwm6 0xxxxxx0x ccapm1 pca module1 mode dbh -- ecom1 capp1 capn1 mat1 tog1 pwm1 eccf1 x 0000000 ccapm7 pca module7 mode dbh pwm7 xxxxxxx0x ccapm2 pca module2 mode dch dte2 ecom2 capp2 capn2 ma t2 tog2 pwm2 eccf2 0 0000000 ---- ---- dc h -- -- -- -- -- -- -- -- ---- ccapm3 pca module3 mode ddh -- ecom3 capp3 capn3 mat3 tog3 pwm3 eccf3 x 0000000 ---- ---- dd h -- -- -- -- -- -- -- -- ---- ccapm4 pca module4 mode deh dte4 ecom4 capp4 capn4 mat4 tog 4 pwm4 eccf4 0 0000000 ---- ---- de h -- -- -- -- -- -- -- -- ---- ccapm5 pca module5 mode dfh -- ecom5 capp5 capn5 mat5 tog5 pwm5 eccf5 x 0000000 ---- ---- df h -- -- -- -- -- -- -- -- ---- acc accumulator e0h 00000000 wdtcr w dt control register e1h wr en nsw enw cl r w widl ps2 ps1 ps0 0 0 000000 ifd isp flash data e2h 11111111 ifadrh isp flash a ddr . high e3h 00000000 ifadrl isp flash addr . low e4h 00000000 ifmt isp mode table e5h gf gf gf gf gf ms . 2 ms . 1 ms . 0 00000 000 scm d isp serial command e6h xxxxxxxx ispcr isp control register e7h ispen sw bs s w rst cfail -- datm2 datm1 datm0 0000 x000 p4 port 4 e8h p4.7 -- p4.5 p4.4 -- -- p4.1 p4.0 1 x 11 xx 11 cl pca base timer low e9h 00000000 ccap0l pca module0 capture low eah 00000000 ccap6l pca module6 compare low eah 00000000 ccap 1 l pca module1 capture low e b h 00000000 ccap7l pca module7 compare low ebh 00000000 ccap 2 l pca module2 capture low e c h 00000000 ---- ---- ec h -- -- -- -- -- -- -- -- ---- ccap3 l pca module3 capture low e d h 00000000 ---- ---- ed h -- -- -- -- -- -- -- -- ---- ccap 4 l pca module4 capture low e e h 00000000 ---- ---- ee h -- -- -- -- -- -- -- -- ----
18 mg82fg5b xx data sheet megawin ccap5 l pca module 5 capture low e f h 00000000 ---- ---- ef h -- -- -- -- -- -- -- -- ---- b b register f0h 00000000 pcapwm0 pca pwm0 mode f2h p0rs1 p0rs0 p0ps2 p0ps1 p0ps0 p0inv epc0h epc0l 00000000 pcapwm6 pca pwm6 mode f2h p6rs1 p6rs0 p6ps2 p6ps1 p6ps0 p6inv epc6h epc6l 0 0000000 pcapwm1 pca pwm1 mode f3h p1rs1 p1rs0 p1ps2 p1ps1 p1ps0 p1inv epc1h epc1l 00000000 pcapwm7 pca pwm7 mode f3h p7rs1 p7rs0 p7ps2 p7ps1 p7ps0 p7inv epc7h epc7l 00000000 pcapwm2 pca pwm2 mode f4h p2rs1 p2rs0 p2ps2 p2ps1 p2ps0 p2inv epc2h epc2l 00000 000 ---- ---- f4 h -- -- -- -- -- -- -- -- ---- pcapwm3 pca pwm3 mode f5h p3rs1 p3rs0 p3ps2 p3ps1 p3ps0 p3inv epc3h epc3l 00000000 ---- ---- f5 h -- -- -- -- -- -- -- -- ---- pcapwm4 pca pwm4 mode f6h p4rs1 p4rs0 p4ps2 p4ps1 p4ps0 p4inv epc4h epc4l 00000 000 ---- ---- f6 h -- -- -- -- -- -- -- -- ---- pcapwm5 pca pwm5 mode f7h p5rs1 p5rs0 p5ps2 p5ps1 p5ps0 p5inv epc5h epc5l 00000000 ---- ---- f7 h -- -- -- -- -- -- -- -- ---- p6 port 6 f8h p6.7 p6.6 p6.5 p6.4 p6.3 p6.2 p6.1 p6.0 11111111 ch pca base tim er high f9h 00000000 ccap0h pca module0 capture high fah 00000000 ccap6h pca module6 compare high fah 00000000 ccap1h pca module1 capture high fbh 00000000 ccap 7 h pca module7 compare high fbh 00000000 ccap2h pca module2 capture high fch 00000000 ---- ---- fc h -- -- -- -- -- -- -- -- ---- ccap3h pca module3 capture high fdh 00000000 ---- ---- fd h -- -- -- -- -- -- -- -- ---- ccap4h pca module4 capture high feh 00000000 ---- ---- fe h -- -- -- -- -- -- -- -- ---- ccap5h pca module5 capture high ffh 00000000 ---- ---- ff h -- -- -- -- -- -- -- -- ----
megawin mg82fg5b xx data sheet 19 4.3. auxiliary sfr map (page p) mg82fg5bxx has an auxiliary sfr page which is indexed by page p and the sfrs ? write is a different way from standard 8051 sfr page. the register s in auxiliary sfr map are addressed by ifmt and scmd like isp/iap access flow . page p has 256 bytes space that can target to 6 physical bytes and 8 logical bytes . the 5 physical bytes include iaplb, ckcon2, ckc on3, pcon2, s pcon 0 and d con0 . the 8 logical bytes include pcon0, pcon1, rtccr, ckcon0, ckcon1, wdtcr, p4 and p6. access on the 8 logical bytes gets the coherence content with the same sfr in page 0~f. please refer section ? 27 page p sfr access ? for more detail information. table 4 ? 3 . auxiliary sfr map (page p) 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8 p6 -- -- -- -- -- -- -- f 0 -- -- -- -- -- -- -- -- e8 p4 -- -- -- -- -- -- -- e0 -- wdtcr -- -- -- -- -- -- d8 -- -- -- -- -- -- -- -- d0 -- -- -- -- -- -- -- -- c8 -- -- -- -- -- -- -- -- c0 -- -- -- -- -- -- -- ckcon0 b8 -- -- -- -- -- -- rtccr ckcon1 b0 -- -- - - -- -- -- -- -- a8 -- -- -- -- -- -- -- -- a0 -- -- -- -- -- -- -- -- 98 -- -- -- -- -- -- -- -- 90 -- -- -- -- -- -- -- pcon1 88 -- -- -- -- -- -- -- 80 -- -- -- -- -- -- -- pcon0 78 -- -- -- -- -- -- -- -- 70 -- -- -- -- -- -- -- -- 68 -- -- -- -- -- -- -- -- 60 -- -- -- -- -- -- -- -- 58 -- -- -- -- -- -- -- -- 50 -- -- -- -- -- -- -- -- 48 spcon0 -- -- -- dcon0 -- -- -- 40 ckcon2 ckcon3 -- -- pcon2 -- -- 38 -- -- -- -- -- -- -- -- 30 -- -- -- -- -- -- -- -- 28 -- -- -- -- -- -- -- -- 20 -- -- -- -- -- -- -- -- 18 -- -- -- -- -- -- -- -- 10 -- -- -- -- -- -- -- -- 08 -- -- -- -- -- -- -- -- 00 -- -- -- iaplb -- -- -- -- 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f
20 mg82fg5b xx data sheet megawin 4.4. auxiliary sfr bit assignment (page p) table 4 ? 4 . auxiliary sfr bit assignment (page p) symbol description addr bit address and symbol reset v alue bit - 7 bit - 6 bit - 5 bit - 4 bit - 3 bit - 2 bit - 1 bit - 0 physical bytes iaplb iap low boundary 03h iaplb6 iaplb5 ia plb4 iaplb3 iaplb2 iaplb1 iaplb0 0 0 1110110 ckcon2 clock control 2 40h xtgs1 xtgs0 xtale ihrcoe mcks1 mcks0 oscs1 oscs0 01010000 ckcon3 clock control 3 41h -- -- fwkp -- mckd1 mckd0 mcds1 mcds0 xx0x0010 pcon2 power control 2 44h awbod1 0 bo1s1 bo1s0 bo1 re ebod1 bo0re 1 0000 0 1 0 1 spcon0 sfr page control 0 48h rtcctl p6ctl p4ctl wrctl ckctl1 ckctl0 pwctl1 pwctl0 0 0000 0 00 dcon0 device contro l 0 4 c h 0 iapo 0 0 0 iorctl rstio ocde 000000 1 1 logical bytes pcon 0 power control 0 87h smod 1 smod0 gf pof 0 gf1 gf0 pd idl 00010000 pcon1 power control 1 97h swrf exrf mcdf rtcf -- bof1 bof0 wdtf 00 0 0x000 rtccr rtc control register beh rtce rtco rtcrl.5 rtcrl.4 rtcrl.3 rtcrl.2 rtcrl.1 rtcrl.0 00111111 ckcon1 clock control 1 bfh -- -- xcks5 xcks4 xcks3 xcks2 xcks1 xc ks0 xx000000 ckcon0 clock control 0 c7h afs enckm ckmis1 ckmis0 ccks sck s 2 sck s 1 scks0 0001 0 000 wdtcr wdt control register e1h wr en nsw enw cl r w widl ps2 ps1 ps0 0 0 000000 p4 port 4 e8h p4.7 -- p4.5 p4.4 -- -- p4.1 p4.0 1 x 11 xx 11 p6 port 6 f8h -- -- -- -- -- -- p6.1 p6.0 xxxxxx 11 sample code of page - p sfr write ifadrh = 0x00; ispcr = ispen; // enable iap/isp ifmt = ms2; // page -p write ifmt =0x04 ifadrl = spcon0; // set page -p sf r address ifd |= ckctl0; // set ckctl 0 scmd = 0x46; // scmd = 0xb9; // ifmt = flash_standby; // iap/isp standby ifmt =0x00 ispcr &= ~ispen;
megawin mg82fg5b xx data sheet 21 5. pin configurations 5.1. package instruction figure 5 ? 1 . mg82fg5bxx ad 32 top view 28 1 2 3 4 5 17 18 19 20 21 22 23 24 6 7 8 27 26 25 31 30 29 9 10 11 12 13 14 15 16 qfn32/ lqfp32 32 vss p1.0 (ain0/t2/t2cko/ twi1_scl/s1mi/kbi4) p1.1 (ain1/vref+/t2ex/twi1_sda /kbi5) p1.2 (ain2/rxd1/kbi6) p1.3 (ain3/txd1/kbi7) rst (p4.7) p4.5 (nint3/ rtcko/ocd_sda/txd0/t1/ t1cko/t2/t2 cko) p4.4 (nint2/beep /ocd_scl/rxd0/t0/t0 cko/t2ex) p6.1 (xtal1/twi 0_sda/nint2) p6.0 (xtal2/ ecki/icko/twi0_scl/nint 3) p2.0 (pwm6/kbi0/nss/pwm0/nint2) p2.1 (eci/pwm7/kbi1/mosi/pwm0/nint3 ) p2.7 (cex5/kbi3) p2.5 (cex3/kbi2) (twi1_scl/nint0/kbi0/rxd0) p3. 0 (twi1_sda/nint1/kbi1/txd0) p3.1 (eci/stwi_sda/s0mi/nint0) p3.2 (cex1/rxd1/stwi_scl_nint1) p3.3 (txd1/cex3/kbi2 /t0cko/t0) p3.4 (cex5/kbi3/s1mi/s1cko/t1cko/t1) p3.5 (n/int1/pwm2/miso/twi0_sda) p4.1 (kbi4/cex0) p2.2 (kbi5/cex1 ) p2.3 (kbi6/cex2) p2.4 (kbi7/cex4) p2.6 (nint0/pwm2/spiclk/twi0_ scl) p4.0 vr0 vdd (nint3/mosi/ain5) p1.5 (s0mi/nint0/miso/ain6) p1.6 (nint2/nss/ain4) p1.4 (nint1/spiclk/ain7) p 1.7
22 mg82fg5b xx data sheet megawin figure 5 ? 2 . m g 82 f g5b xx a s28 top view sop 28 1 2 3 4 5 6 7 8 9 10 15 16 17 18 19 20 21 22 23 24 11 12 13 14 25 26 27 28 p1.7 (ain7/ spiclk/nint1) vdd vr0 vss (kbi4/s1mi/twi1_scl/t2cko/t2/ain0) p1.0 (kbi5/twi1_sda /t2ex/vref+/ain1) p1.1 (kbi6/rxd1/ain2) p1.2 (kbi7/txd1/ain3) p1.3 p2.2 (cex0/ kbi4) p2.4 (cex2/kbi6) p2.6 (cex4/kbi7) p3.3 (nint1/ stwi_scl/rxd1/cex 1) p3.4 (t0/ t0cko/kbi2/txd 1/cex3) p4.1 (twi0_sda/miso/pwm2/nint1) p4.0 (twi0_scl/spiclk/pwm2/nint0) rst (p4.7) (nint2/twi0_sda/xtal 1) p6.1 (nint3/twi0_scl/icko/ecki/xtal2) p6.0 (nint2/pwm0/ nss/kbi0/pwm6) p2.0 (nint3/pwm0/mosi/kbi1/pwm7/eci) p2.1 (nint3/mosi/ain5) p1.5 (s0mi/nint0/miso/ain6) p1.6 (nint2/nss/ain4) p 1.4 p3.0 (rxd0/kbi0/nint0/twi1_scl) p3.1 (txd0/kbi1/nint1/twi1 _sda) p4.5 (nint3/ rtcko/ocd_sda/txd0/ t1/t1cko/t2/t2cko ) p4.4 (nint2/beep /ocd_scl/rxd0/ t0/t0cko/t2ex) p3.5 (t1/t1cko/s1cko/s1mi/kbi3/cex5) figure 5 ? 3 . m g 82 f g5b xx a s 2 0 top view sop 20 1 2 3 4 5 6 7 8 9 10 15 16 17 18 19 20 11 12 13 14 (nint1/spiclk/ain7) p1.7 vdd vr0 vss (kbi4/s1mi/twi1_scl/t2cko/t2/ain0) p1.0 (kbi5/twi1_sda/t2ex/vref+/ain1) p1.1 p2.2 (cex0/kbi4) p2.4 (cex2/kbi6) p3.3 (nint1/stwi_scl/rxd1/cex1) p3.4 (t0/t0cko/kbi2/txd1/cex3) rst (p4.7) (nint2/twi0_ sda/xtal1) p6.1 (nint3/twi0_scl/icko/ecki/xtal2) p 6.0 (nint3/mosi/ain5) p1.5 p3.0 (rxd0/kbi0/nint0/twi1_scl) p3.1 (txd0/kbi1/nint1/twi1_sda) p4.5 (nint3/rtcko/ocd_sda/txd0/ t1/t1cko/t2/t2cko) p4.4 (nint2/beep/ocd_scl/rxd0/t0/t0cko/t2 ex) p3.5 (t1/t1cko/s1cko/s1mi/kbi3/cex5) (s0mi/nint 0/miso/ain6) p1.6 figure 5 ? 4 . m g 82 f g5b xx a l 16 top view (s0mi/nint0/miso/ain6) p1.6 sop16 1 2 3 4 5 6 7 8 9 10 15 16 11 12 13 14 vdd vr0 vss (kbi4/s1mi/twi 1_scl/t2cko/t2/ain0) p1 .0 (kbi5/twi1_sda/t2ex/vref+/ain1) p1.1 p2.2 (cex0/kbi4) p2.4 (cex2/kbi6) p3.3 (nint1/stwi_ scl/rxd1/cex1) rst (p4.7) (nint2/twi0_sda/xtal1) p6.1 (nint3/twi0_scl/icko/ecki/xtal 2) p6.0 p4.5 (nint3/rtcko/ocd_sda/txd0/t1 /t1cko/t2/t2 cko) p4.4 (nint2/beep/ocd_scl/rxd0/t0 /t0cko/t2ex) p3.0 (rxd0/kbi0/ nint0/twi1_scl) p3.1 (txd0/kbi1 /nint1/twi1_sda)
megawin mg82fg5b xx data sheet 23 5.2. pin description table 5 ? 1 . pin description mnemonic pin number i/o type description 32 - pin lqfp 28 - pin s op 20 - pin sop 16 - pin s sop p1.0 ( ain0 ) (t2 ) (t2cko) (twi1_scl) (s1mi) 29 8 6 6 i/o * port 1 . 0. * ain0: adc channel - 0 analog input. * t2: timer/counter 2 external clock input. * t2cko : timer 2 programmable clock output . * twi1_scl: serial clock of twi1 * s 1 mi: spi master input on uart 1 . p1.1 ( ain1 ) ( t2ex ) (twi1_sda) 30 9 7 7 i/o * port 1 .1 . * ain1: adc channel - 1 analog input. * t2ex: timer/counter 2 external control input. * twi1_sda: serial data of twi1. p1.2 ( ain2 ) ( rxd 1) 31 10 i/o * port 1 . 2. * ain 2: adc channel - 2 analog input. * rxd 1 : uart 1 serial input port. p1.3 ( ain3 ) ( txd 1) 32 11 i/o * port 1 . 3. * ain3: adc channel - 3 analog input. * txd 1 : uart 1 serial output port. p1.4 ( ain4 ) (n ss ) 1 12 i/o * port 1 . 4. * ain4: adc channel - 4 analog input. * n ss: spi slave select. p1.5 ( ain5 ) ( mosi ) 2 13 8 i/o * port 1 . 5. * ain5: adc channel - 5 analog input. * mosi: spi master out & slave in. p1.6 ( ain6 ) ( miso ) 3 14 9 8 i/o * port 1 . 6. * ain6: adc channel - 6 analog input. * miso: spi master in & slave out. p1.7 ( ain7 ) ( spiclk) 4 15 10 i/o * port 1 . 7. * ain7: adc channel - 7 analog input. * spiclk: spi clock, output for master and input for slave. p2.0 (pwm6) (kbi0) 22 3 i/o * port 2 . 0. * pwm 6 : pca module - 6 pwm 6 output . * kbi0: keypad input 0. p2.1 ( eci ) (pwm7) (kbi1) 23 4 i/o * port 2 .1 . * eci: pca external clock input. * pwm 7 : pca module - 7 pwm 7 output . * kbi1: keypad input 1. p2.2 ( cex0 ) (kbi4) 5 16 11 9 i/o * port 2 . 2. * cex0: pca module - 0 external i/o. * kbi4: keypad input 4. p2.3 ( cex 1) (kbi5) 6 i/o * port 2 . 3. * cex 1 : pca module - 1 external i/o. * kbi5: keypad input 5. p2.4 ( cex 2) (kbi6) 7 17 12 10 i/o * port 2 . 4. * cex 2 : pca module - 2 external i/o. * kbi6: keypad input 6. p2.5 ( cex 3) (kbi2) 24 i/o * port 2 . 5. * cex 3 : pca module - 3 external i /o. * kbi2: keypad input 2. p2.6 ( cex 4) (kbi7) 8 18 i/o * port 2 . 6. * cex 4 : pca module - 4 external i/o. * kbi7: keypad input 7. p2.7 ( cex 5) (kbi3) 25 i/o * port 2 . 7. * cex 5 : pca module - 5 external i/o. * kbi3: keypad input 3. p3.0 ( rxd 0) 9 19 13 11 i /o * port 3 . 0. * rxd 0 : uart0 serial input port. p3.1 ( txd 0) 10 20 14 12 i/o * port 3 . 1. * txd 0 : uart0 serial output port. p3.2 (n int0 ) (s0mi) 11 i/o * port 3 . 2. * n int0: external interrupt 0 input. * s 0 mi: spi master input on uart 0 .
24 mg82fg5b xx data sheet megawin p3.3 (n int1 ) 12 2 1 15 13 i/o * port 3 . 3. * n int1: external interrupt 1 input. p3.4 (t0 ) ( t0cko ) 13 22 16 i/o * port 3. 4. * t0: timer/counter 0 external input. * t0cko: timer 0 programmable clock out put . p3.5 (t1 ) (t1 cko ) (s1cko) 14 23 17 i/o * port 3 . 5. * t1: timer/cou nter 1 external input. * t1 cko: timer 1 programmable clock out put . * s1cko: s1brt programmable c lock o utput . p4.0 (twi 0 _scl) 15 24 i/o * port 4 . 0. * twi 0 _scl: serial clock of twi 0 . p4.1 (twi 0 _sda) 16 25 i/o * port 4 . 1. * twi 0 _sda: serial data of twi 0 . p4.4 (n int2 ) (beep) ( ocd_scl ) 18 27 19 15 i/o * port 4 . 4. * n int 2 : external interrupt 2 input. * beep : beeper output. * ocd_scl: ocd interface, serial clock. p4.5 (n int3 ) (rtcko) (ocd_sda) 19 28 20 16 i/o * port 4 . 5. * n int3: external interrupt 3 input . * rtcko : rtc programmable clock output. * ocd_sda: ocd interface, serial data. p6.0 ( xtal2 ) (ecki) (icko) 21 2 2 2 i/o o i o * port 6.0 . * xtal 2: ou tput of on - chip crystal oscillating circuit. * ecki: in external clock input mode, this is clock input pi n. * icko: enable ihrco/ilrco output. p6.1 ( xtal1 ) 20 1 1 1 i /o i * port 6.1. * xtal1 : in put of on - chip crystal oscillating circuit. rst (p4.7) 17 26 18 14 i * rst: external reset input, high active. * port 4 .7 . vr0 27 6 4 4 i/o * vr0. voltage reference 0. connect 0.1uf and 4.7uf to vss. vdd 28 7 5 5 p power supply input. vss 26 5 3 3 g ground, 0 v reference.
megawin mg82fg5b xx data sheet 25 5.3. alternate function redirection many i/o pins, in addition to their normal i/o function, also serve the alternate function for internal peri pherals. for the peripherals keypad interrupt (kbi) , pca, spi , uart0, uart 1, twi 0 , twi1 and external interrupts (nint0~3) , port 1 , port 2 , port 3, port 4 and port 6 serve the alternate function in the default state. however, the user may select port 4 and port 5 to serve their alternate function by setting the corresponding control bits p4kb, p4pca, p 5 spi and p4s 1 in auxr1 register. it is especially useful when the package s more than 40 pins are adopted. note that only one of the four control bits can be se t at any time. auxr0: auxiliary register 0 sfr page = 0~f sfr address = 0xa1 reset = 000 x - 0000 7 6 5 4 3 2 1 0 p60fc1 p60fc0 p60fd t0xl p4fs1 p4fs0 int1h int0h r/w r/w r/w r/w r/w r/w r/w r/w bit 7~6: p6.0 function configured control bit 1 and 0. t he two bits only act when internal rc oscillator (ihrco or ilrco) is selected for system clock source. in crystal mode, xtal2 and xtal1 are the alternated function of p6.0 and p6.1. in external clock input mode, p6.0 is the dedicated clock input pin . in in ternal oscillator condition, p6.0 provides the following selections for gpio or clock source generator. when p60oc[1:0 ] index to non - p6.0 gpio function, p6.0 will drive the on - chip rc oscillator output to provide the clock source for other devices. p60oc[ 1:0] p60 function i/o mode 00 p60 by p6m0.0 01 mck by p6m0.0 10 mck/2 by p6m0.0 11 mck/4 by p6m0.0 please refer section ? 9 system clock ? to get the more detailed cl ock information. for clock - out on p 6 .0 function, it is recommended to set p 6 m0.0 to ? 1 ? which selects p 6 .0 as push - push output mode. bit 5: p60fd, p6.0 fast driving. 0: p6.0 output with default driving. 1: p6.0 output with fast driving enabled. if p6.0 is configured to clock output, enable this bit when p6.0 output frequency is more than 12mhz at 5v application or more than 6mhz at 3v application. bit 3~2: p4.4 and p4.5 alternated function selection. p4fs[1:0] p4.4 p4.5 00 p4.4 p4.5 01 rxd0 txd0 10 t0/ t0cko t1/t1cko 11 t2ex t2/t2cko auxr1 : auxiliary control register 1 sfr page = 0~f sfr address = 0xa2 reset = 0000 - 0000 7 6 5 4 3 2 1 0 p1kbih p3kbil p4spi p3s1 p3s1mi p6twi 0 p3cex dps r/w r/w r/w r/w r /w r /w r /w r/w bit 7: p1kbih, kbi high nibb le port selection on p1.3, p1.2, p1.1 and p1.0. p1kbih kbi.7~4 0 p2.6, p2.4, p2.3, p2.2 1 p1.3, p1.2, p1.1, p1.0 bit 6: p3kbil, kbi low nibble port selection on p3.5, p3.4, p3.1 and p3.0. p3kbil kbi.3~0 0 p2.7, p2.5, p2.1, p2.0 1 p3.5, p3.4, p3.1, p3 .0
26 mg82fg5b xx data sheet megawin bit 5: p4spi, spi interface on p 4.1~p4.0 and p2.1~p2.0 p4spi nss mosi miso spiclk 0 p1.4 p1.5 p1.6 p1.7 1 p2.0 p2.1 p4.1 p4.0 bit 4: p3s1, serial port 1 (uart1) function on p3.3 and p3.4 if p3cex (auxr1.1) is disabled. p3s1 rxd1 txd1 0 p1.2 p1.3 1 p3.3 p3.4 bit 3: p3s1mi, s1mi function on p 3 . 5 . s1mi is the spi serial data input of the s1 mode 4 (spi master). p3s1mi s1mi 0 p1.0 1 p3.5 bit 2: p6twi 0 , twi 0 function on p6. the function is valid when p60oc[1:0] is equal to ? 00? . p6twi 0 twi 0 _scl twi 0 _sda 0 p4.0 p4.1 1 p6.0 p6.1 bit 1: p3cex, cex5, cex3 and cex1 function on p3.5, p3.4 and p3.3. p3cex cex5 cex3 cex1 0 p2.7 p2.5 p2.3 1 p3.5 p3.4 p3.3 auxr2: auxiliary register 2 sfr page = 0~f sfr address = 0xa3 reset = 0000 - 0000 7 6 5 4 3 2 1 0 int3is1 int3is0 int2is1 int2is0 t1x12 t0x12 t1ckoe t0ckoe r/w r/w r/w r/w r/w r/w r/w r/w bit 7~6: int3is1~0, nint3 input selection bits which function is defined as following table. int3is1~0 nint3 00 p4.5 01 p2.1 10 p1.5 11 p6.0 bit 5~4: int2is1~0, nint2 input selection bits which function is defined as following table. int2is1~0 nint2 00 p4.4 01 p2.0 10 p1.4 11 p6.1 auxr3: auxiliary register 3 sfr page = 0~f sfr address = 0xa4 reset = 0000 - 0000 7 6 5 4 3 2 1 0 staf stof bpoc1 bpoc0 gf p1s0mi p3eci p3twi1 r/w r/w r/w r/w r/w r/w r/w r/w
megawin mg82fg5b xx data sheet 27 bit 2: p1s0mi, s0mi function on p1.6. p1s0mi s0mi 0 p3.2 1 p1.6 bit 1: p3eci, eci function on p3.2. p3eci eci 0 p2.1 1 p3.2 bit 0: p3twi1, twi1 function on p3. p3twi1 twi1_scl twi1_s da 0 p1.0 p1.1 1 p3.0 p3.1
28 mg82fg5b xx data sheet megawin 6. 8051 cpu function description 6.1. cpu register psw : program status word sfr page = 0~f sfr address = 0xd0 reset = 0000 - 0000 7 6 5 4 3 2 1 0 cy ac f0 rs1 rs0 ov f1 p r/w r/w r/w r/w r/w r/w r/w r/w cy: carry bit. ac: a uxiliary carry bit. f0: general purpose flag 0. rs1: register bank select bit 1. rs0: register bank select bit 0. ov: overflow flag. f1: general purpose flag 1. p: parity bit. the program status word (psw) contains several status bits that reflect the cur rent state of the cpu. the psw, shown above , resides in the sfr space. it contains the carry bit, the auxiliary carry(for bcd operation), the two register bank select bits, the overflow flag, a parity bit and two user - definable status flags. the carry bit , other than serving the function of a carry bit in arithmetic operations, also serves as the ?accumulator? for a number of boolean operations. the bits rs0 and rs1 are used to select one of the four register banks shown in section ? 7.2 on - chip data ram ? . a number of instructions refer to these ram locations as r0 through r7. the parity bit reflects the number of 1s in the accumulator. p=1 if the accumulator contains a n odd number of 1s and otherwise p=0. s p: stack pointer sfr page = 0~f sfr address = 0x81 reset = 0000 - 0111 7 6 5 4 3 2 1 0 sp.7 sp.6 sp.5 sp.4 sp.3 sp.2 sp.1 sp.0 r/w r/w r/w r/w r/w r/w r/w r/w the stack pointer holds the location of the top of the stack. the stack pointer is incremented before every push operation. the sp register defaults to 0x07 after reset. dpl: data pointer low sfr page = 0~f sfr address = 0x82 reset = 0000 - 0000 7 6 5 4 3 2 1 0 dpl.7 dpl.6 dpl.5 dpl.4 dpl.3 dpl.2 dpl.1 dpl.0 r/w r/w r/w r/w r/w r/w r/w r/w the dpl register is the low byte of the 16 - bit dptr. dptr is used to access indirectly addressed xram and flash memory. dph: data pointer high sfr page = 0~f sfr address = 0x83 reset = 0000 - 0000 7 6 5 4 3 2 1 0 dph.7 dph.6 dph.5 dph.4 dph.3 dph.2 dph.1 dph.0 r/w r/w r/w r/w r/w r/w r/w r/w
megawin mg82fg5b xx data sheet 29 the dph register is the high byte of the 16 - bit dptr. dptr is used to access indirectly addressed xram and flash memory. acc: accumulator sfr page = 0~f sfr address = 0xe 0 reset = 0000 - 0000 7 6 5 4 3 2 1 0 acc.7 acc.6 acc.5 acc.4 acc.3 acc.2 acc.1 acc.0 r/w r/w r/w r/w r/w r/w r/w r/w this register is the accumulator for arithmetic operations. b: b register sfr page = 0~f sfr address = 0xf0 reset = 0000 - 0000 7 6 5 4 3 2 1 0 b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 r/w r/w r/w r/w r/w r/w r/w r/w this register serves as a second accumulator for certain arithmetic operations. 6.2. cpu timing the mg82fg5bxx is a single - chip microcontroller based on a high performance 1 - t architecture 80c51 cpu that has an 8051 compatible instruction set , and executes instructions in 1~7 clock cycles (about 6~7 times the rate of a standard 8051 device) . it employs a pipelined architecture that greatly increases its instruction throughput o ver the standard 8051 architecture. the instruction timing is different than that of the standard 8051. in many 8051 implementations, a distinction is made between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in l ength. however, the 1t - 80c 51 implementation is based solely on clock cycle timing. all instruction timings are specified in terms of clock cycles. for more detailed information about the 1t - 80c51 instructions, please refer section ? 32 instruction set ? which includes the mnemonic, number of bytes, and number of clock cycles for each instruction.
30 mg82fg5b xx data sheet megawin 6.3. cpu addressing mode direct addressing(dir) in direct addressing the operan d is specified by an 8 - bit address field in the instruction. only internal data ram and sfrs can be direct addressed. indirect addressing(ind) in indirect addressing the instruction specified a register which contains the address of the operand. both inte rnal and external ram can be indirectly addressed. the address register for 8 - bit addresses can be r0 or r1 of the selected bank, or the stack pointer. the address register for 16 - bit addresses can only be the 16 - bit data pointer register ? dptr. reg ister instruction(reg) the register banks, containing registers r0 through r7, can be accessed by certain instructions which carry a 3 - bit register specification within the op - code of the instruction. instructions that access the registers this way are cod e efficient because this mode eliminates the need of an extra address byte. when such instruction is executed, one of the eight registers in the selected bank is accessed. register - specific instruction some instructions are specific to a certain register. for example, some instructions always operate on the accumulator or data pointer, etc. no address byte is needed for such instructions. the op - code itself does it. immediate constant(imm) the value of a constant can follow the op - code in the program memo ry. index addressing only program memory can be accessed with indexed addressing and it can only be read. this addressing mode is intended for reading look - up tables in program memory. a 16 - bit base register(either dptr or pc) points to the base of the t able, and the accumulator is set up with the table entry number. another type of indexed addressing is used in the conditional jump instruction. in conditional jump, the destination address is computed as the sum of the base pointer and the accumulator.
megawin mg82fg5b xx data sheet 31 7. memory organization like a ll 80c51 devices , the mg82fg5bxx has separate address spaces for p rogram and d ata m emory . the logical separation of program and data memory allows the data memory to be accessed by 8 - bit addresses, which can be quickly stored an d manipulated by the 8 - bit cpu. program memory (rom) can only be read, not written to. there can be up to 32 k /16k /8k bytes of program memory. in the mg82fg5bxx , all the p rogram memory are on- chip flash memory, and without the capability of accessing exter nal program memory because of no external access enable (/ea) and p rogram s tore en able (/psen) signals designed. data m emory occupies a separate address space from p rogram m emory. in the mg82fg5bxx , the re are 256 bytes of internal scratch - pad ram and 1792 /768 /256 bytes of on - chip expanded ram(xram) . 7.1. on - chip program flash program memory is the memory which stores the program codes for the c pu to execute, as shown in figure 7 ? 1 . after reset, the cpu begins executi on from location 0000h, where should be the starting of the user?s application code. to service the interrupts, the interrupt service locations (called interrupt vectors) should be located in the program memory. each interrupt is assigned a fixed location in the program memory. the interrupt causes the cpu to jump to that location, where it commences execution of the service routine. external interrupt 0, for example, is assigned to location 0003h. if external interrupt 0 is going to be used, its service ro utine must begin at location 0003h. if the interrupt is not going to be used, its service location is available as general purpose program memory. the interrupt service locations are spaced at an interval of 8 bytes: 0003h for external interrupt 0, 000bh for timer 0, 0013h for external interrupt 1, 001bh for timer 1, etc. if an interrupt service routine is short enough (as is often the case in control applications), it can reside entirely within that 8 - byte interval. longer service routines can use a jump instruction to skip over subsequent interrupt locations, if other interrupts are in use. figure 7 ? 1 . program memory 0000 h 0003h 0013h 001bh interrupt locations reset 000bh 8 bytes program memory 32 k : 7 fffh
32 mg82fg5b xx data sheet megawin 7.2. on - chip data ram figure 7 ? 2 shows the in ternal and external data memory spaces available to the mg82fg5bxx user. internal data memory can be divided into three blocks, which are generally referred to as the lower 128 bytes of ram, the upper 128 bytes of ram, and the 128 bytes of sfr space. inter nal data memory addresses are always 8 - bit wide, which implies an address space of only 256 bytes. direct addresses higher than 7fh access the sfr space; and indirect addresses higher than 7fh access the upper 128 bytes of ram. thus the sfr space and the u pper 128 bytes of ram occupy the same block of addresses, 80h through ffh, although they are physically separate entities. the lower 128 bytes of ram are present in all 80c51 devices as mapped in figure 7 ? 3 . the l owest 32 bytes are grouped into 4 banks of 8 registers. program instructions call out these registers as r0 through r7. two bits in the program status word (psw) select which register bank is in use. this allows more efficient use of code space, since regi ster instructions are shorter than instructions that use direct addressing. the next 16 bytes above the register banks form a block of bit - addressable memory space. the 80c51 instruction set includes a wide selection of single - bit instructions, and the 128 bits in this area can be directly addressed by these instructions. the bit addresses in this area are 00h through 7fh. all of the bytes in the lower 128 can be accessed by either direct or indirect addressing while the upper 128 can only be accessed by i ndirect addressing. figure 7 ? 4 gives a brief look at the special function register (sfr) space. sfrs include the port latches, timers, peripheral controls, etc. these registers can only be accessed by direct addre ssing. sixteen addresses in sfr space are both byte - and bit - addressable. the bit - addressable sfrs are those whose address ends in 0h or 8h. figure 7 ? 2 . mg82fg5b32 data memory upper 128 bytes internal 256 bytes sram addressable by indirect addressing only addressable by direct and indirect addressing lower 128 bytes addressable by direct addressing ( sfrs ) sfrs 00 h 7 fh 80 h ffh ffh 80 h addressable by indirect external addressing on - chip xram 1792 bytes 1792 bytes 0000 h 06 ffh
megawin mg82fg5b xx data sheet 33 figure 7 ? 3 . lower 128 bytes of internal ram bank 0 lower 128 bytes of internal sram bank 1 bank 2 bank 3 bit addressable 00h 08h 10h 18h 20h 07h 0fh 17h 1fh 2fh 7fh 30h reset value of stack pointer four banks of 8 registers r0~r 7 figure 7 ? 4 . sfr space port 0 80 h port 1 90 h port 2 a 0 h port 3 b 0 h psw d 0 h acc e 0 h ffh 1 . i / o ports are register mapping 2 . addresses that end in 0h or 8h are also bit-addressable - i/o ports - psw - accumulator (etc.)
34 mg82fg5b xx data sheet megawin 7.3. on - chip expanded ram (xram) to access the on - chip expanded ram (xram), refer to figure 7 ? 2 , the 1792 /768 /256 bytes of xram (0000h to 06 ffh ) are indirectly accessed by move external instruction, ?movx @ri? and ?movx @dptr?. for keil - c51 compiler, to assign the variables to be located at xram, the ?pdata? or ?xdata ? definition should be used. after being compiled, the variables declared by ?pdata? and ?xdata? will become the memories accessed by ?movx @ri? and ?movx @dptr?, respectively. thus the mg82fg5bxx hardware can access them correctly.
megawin mg82fg5b xx data sheet 35 7.4. declaration identifi ers in a c51 - compiler the declaration identifiers in a c51 - compiler for the various mg82fg5bxx memory spaces are as follows: data 128 bytes of internal data memory space (00h~7fh); accessed via direct or indirect addressing, using instructions other than movx and movc. all or part of the stack may be in this area. idata indirect data; 256 bytes of internal data memory space (00h~ffh) accessed via indirect addressing using instructions other than movx and movc. all or part of the stack may be in this area . this area includes the data area and the 128 bytes immediately above it. sfr special function registers; cpu registers and peripheral control/status registers, accessible only via direct addressing. xdata external data or on - chip expanded ram (xram); d uplicates the classic 80c51 64kb memory space addressed via the ?movx @dptr? instruction. the mg82fg5bxx has 1792 /768 /256 bytes of on - chip xdata memory. pdata paged (256 bytes) external data or on - chip expanded ram; duplicates the classic 80c51 256 bytes memory space addressed via the ?movx @ri? instruction. the mg82fg5bxx has 256 bytes of on - chip p data memory which is shared with on - chip xdata memory . code 32k /16k/8k bytes of program memory space; accessed as part of program execution and via the ?movc @ a+dtpr? instruction. the mg82fg5bxx has 32k /16k /8k bytes of on - chip code memory.
36 mg82fg5b xx data sheet megawin 8. dual data pointer register (dptr) the dual dptr str ucture as shown in figure 8 ? 1 is a way by which the chip can specify the addre ss of an external data memory location. there are two 16 - bit dptr registers that address the external memory, and a single bit called dps (auxr 1 .0) that allows the program code to switch between them. figure 8 ? 1 . dual dptr dptr1 dptr0 auxr1(a2h) external data memory (83h) (82h) dpl dph dpl dph dps dps=0 dps=1 dptr instructions the six instructions that refer to dptr currently selected using the dps bit are as follows: inc dptr ; increments the data pointer by 1 mov dptr,#data16 ; loads the dptr with a 16 - bit constant mov a,@a+dpt r ; move code byte relative to dptr to acc movx a,@dptr ; move external ram (16 - bit address) to acc movx @dptr,a ; move acc to external ram (16 - bit address) jmp @a+dptr ; jump indirect relative to dptr auxr1 : auxiliary control register 1 sfr page = 0~f sfr address = 0xa2 reset = 0000 - 0000 7 6 5 4 3 2 1 0 p1kbih p3kbil p4spi p3s1 p3s1mi p6twi p3cex dps r/w r/w r/w r/w r /w r /w r /w r/w bit 0: dps, dptr select bit . u se to switch between dptr0 and dptr1. 0: select dptr0. 1: select dptr1. dps se lected dptr 0 dptr0 1 dptr1
megawin mg82fg5b xx data sheet 37 9. system clock there are four clock sources for the system clock: internal high - frequency rc oscillator (ihrco), external crystal oscillator , internal low - frequency rc oscillator (ilrco) and external clock input . figure 9 ? 1 shows the structure of the system clock in mg82fg5bxx . the mg82fg5bxx always boots from ihrco on 1 2 mhz and reserves crystal pads as p6.0/p6.1 gpio function. software can select the oscin input on one of the four clock sources by application required and switches them on the fly. but software needs to settle the clock source stably before clock switching. if software selects external crystal mode, port pin of p6.0 and p6.1 will be assigned to xtal2 and xtal1. and p6.0/p6.1 gpio function will be inhibited. in external clock input mode (ecki), the clock source comes from p6.0 input and p6.1 still reserves gpio function. after set xtale (ckcon2.5) to enable external crystal oscillating, xtor (ckcon1.7) will be set by hardware to indicate the crystal oscillating is stable for software to switch the oscin on it. xtor is read only. mcu must poll this bit before switching the crystal oscillator as system clock source. the built - in ihrco provides two kinds of frequency fo r software selected. another frequency is 11.059mhz by software setting afs on ckcon0.7. both of 12 mhz and 11. 059 mhz in ihrco provide high precision frequency for system clock source. to find the detailed ihrco performance, please refer section ? 31.4 ihrco characteristics ? ). in ihrco mode, p6.0 can be configured to internal mck output or mck /2 and mck /4 for system application. the built - in i l rco provides the low power and low speed fre quency a bout 32k hz to wdt and system clock source. mcu can selects the ilrco to system clock source by software for low power operation. to find the detailed ihrco performance, please refer section ? 31.5 ilrco characteristics ? ). in ilrco mode, p6.0 can be configured to internal mck output or mck /2 and mck /4 for system application. the mg82fg5bxx device includes a clock multiplier (ckm) to generate the high speed clock fo r system clock source. ckm applied in mg82fg5bxx is shown in figure 9 ? 1 and its typical input frequency is around 6mhz. before enable ckm, software must configure the ckmis1~0 (ckcon.5~4) to get the reasonable ckm i frequency for ckm input source. ckm can generate 4/5.33/8 times frequency of ckmi and setting mcks1~0 (ckcon2.3~2) selects different ckm outputs on mck to provide the high speed operation on mcu without high - frequency clock source. to find the detailed c km performance, please refer section ? 31.6 ckm characteristics ? ). the system clock, sysclk , is obtained from one of these four clock sources through the clock divider, as shown in figure 9 ? 1 . the user can program the divider control bits sck s 2~sck s 0 (in ckco n 0 register) to get the desired system clock. the maximum frequency of sysclk is 50mhz in mg82fg5bxx . software must configure the the cpu clock, cpuclk, is
38 mg82fg5b xx data sheet megawin 9.1. clock structure figure 9 ? 1 presents the principal clock systems in the mg82fg5bxx . the system clock can be sourced by the external oscillator circuit or either internal oscillator. figure 9 ? 1 . system clock ihrco xcks [ 5 : 0 ] ( ckcon 1 . 5 ~ 0 ) scks [ 2 : 0 ] ( ckcon 0 . 2 ~ 0 ) xtal 1 ( p 6 . 1 ) xtal 2 ( p 6 . 0 ) oscs [ 1 : 0 ] ( ckcon 2 . 1 ~ 0 ) isp / iap logic oscin 0 1 2 3 p 6 . 0 sfr 4 2 p 60 oc [ 1 : 0 ] ( auxr 0 . 7 ~ 6 ) p 6 . 0 ( xtal 2 ) 0 1 2 3 ilrco p 6 . 0 ( ecki ) ihrcoe ( ckcon 2 . 4 ) xtale ( ckcon 2 . 5 ) enable enable 1 2 4 6 clock multiplier ckmi ( 5 ~ 6 . 5 mhz ) ckmis [ 1 : 0 ] ( ckcon 0 . 5 ~ 4 ) 12 mhz enckm ( ckcon 0 . 6 ) 0 1 2 3 ckmi x 4 ckmi x 5 . 33 00 : if oscin = 5 ~ 6 . 5 mhz 01 : if oscin = 10 ~ 13 mhz ( default ) 10 : if oscin = 20 ~ 26 mhz 11 : if oscin = 30 ~ 39 mhz 00 : oscin = ihrco ( default ) 01 : oscin = xtal 10 : oscin = ilrco 11 : oscin = ecki mcks [ 1 : 0 ] ( ckcon 2 . 3 ~ 2 ) 00 : mck = oscin ( default ) 01 : mck = 24 mhz ( if ckmi = 6 mhz ) 10 : mck = 32 mhz ( if ckmi = 6 mhz ) 11 : mck = 48 mhz ( if ckmi = 6 mhz ) 00 : p 6 . 0 gpio 01 : mck output 10 : mck / 2 output 11 : mck / 4 output 32 khz 0 ~ 25 mhz mck 0 ~ 40 mhz oscin ckmi x 8 11 . 059 mhz 0 1 afs ( ckcon 0 . 7 ) xtor enable ( ckcon 1 . 7 ) ( system clock ) ( 50 mhz max .) sysclk clock default path 1 2 4 8 mckd [ 1 : 0 ] ( ckcon 3 . 3 ~ 2 ) 00 : pck = mck ( default ) 01 : pck = mck / 2 10 : pck = mck / 4 11 : pck = mck / 8 mckdo 1 2 ( cpu clock ) ( 25 mhz max .) cpuclk ccks ( ckcon 0 . 3 )
megawin mg82fg5b xx data sheet 39 9.2. clock register ckcon 0 : clock control register 0 sfr page = 0~f & p sfr address = 0xc7 reset = 0001 - 0 000 7 6 5 4 3 2 1 0 afs enckm ckmis1 ckmis0 ccks scks2 scks1 scks0 r/ w r /w r /w r /w r/ w r/w r/w r/w bit 7: afs, alternated frequency selection. 0: select ihrco on 12mhz. 1: select ihrco on 11.059mhz. bit 6: enckm, enable clock multiplier (x8) 0: disable the x8 clock multiplier. 1: enable the x8 clock multiplier. bit 5~4: ckmis1 ~ c kmis0, clock multiplier input selection. ckmis [ 1 :0] clock multiplier input selection 0 0 oscin/1 (when oscin 5 ~ 6.5 mhz) 0 1 oscin/2 (when oscin 10 ~ 13 mhz) 1 0 oscin/4 (when oscin 20 ~ 2 6 mhz) 1 1 oscin/6 (when oscin 30 ~ 39 mhz) bit 3: ccks, cpu clock select. 0: select cpu clock as sysclk. 1: select cpu clock as sysclk/2. bit 2~0: scks2 ~ scks0, programmable system clock selection . scks [ 2 :0] system clock 0 0 0 mck/1 0 0 1 mck/2 0 1 0 mck/4 0 1 1 mck/8 1 0 0 mck/16 1 0 1 mck/32 1 1 0 mck/64 1 1 1 mck/128 ckcon 1 : clock control register 1 sfr page = 0~f & p sfr address = 0xbf reset = 0 x00 - 1 0 11 7 6 5 4 3 2 1 0 xtor -- xcks5 xcks4 xcks3 x cks2 x cks1 x cks0 r w r /w r /w r /w r/w r/w r/w bit 7: xtor, crystal oscillating read y. read only. 0: crystal oscillating not ready. 1: crystal oscillating ready. when xtale is enabled, xtor reports the crystal oscillator reached start - up count. bit 6: reserved. software must write ? 0 ? on this bit when ckcon1 is written. bit 5 ~0: this is set the oscin frequency value to define the time base of isp/iap programming. fill with a proper value according to oscin, as listed below. [xcks 5 ~xcks0] = oscin ? 1 , w here oscin=1~ 40 (mhz ) . for examples,
40 mg82fg5b xx data sheet megawin (1) if oscin=12mhz, then fill [xcks 5 ~xcks0] with 11, i.e., 0 0 - 1011b. (2) if oscin=6mhz, then fill [xcks 5 ~xcks0] with 5, i.e., 0 0 - 0101b. oscin xcks [4:0] 1mhz 0 0 - 0000 2mhz 0 0 - 0001 3mhz 0 0 - 0010 4mhz 0 0 - 0011 ?? ?? ?? ?? 38mhz 10 - 0101 39mhz 10 - 0110 40mhz 10 - 0111 the default value of xcks= 00 - 101 1 for oscin= 1 2 mhz. ckcon 2 : clock control register 2 sfr page = p only sfr address = 0x40 reset = 0101 - 0000 7 6 5 4 3 2 1 0 xtgs1 xtgs0 xtale ihrcoe mcks1 mcks0 oscs1 oscs0 r/w r/w r/w r/w r/w r/ w r/ w r/ w bit 7 ~6: xtgs1~xtgs0 , osc driving control r egister. xtgs1 , xtgs 0 gain define 0, 0 gain for 32.768k 0 , 1 gain for 2mhz ~ 25mhz others reserved bit 5: xtale, external crystal(xtal) enable. 0: disable xtal oscillating circuit. in this case, xtal2 and xtal1 behave as port 6.0 and port 6.1. 1: ena ble xtal oscillating circuit. if this bit is set by cpu software , software pools the xtor (ckcon1.7) true to indicate the crystal oscillator is ready for oscin clock selected. bit 4: ihrcoe, internal high frequency rc oscillator enable. 0: disable interna l high frequency rc oscillator. 1: enable internal high frequency rc oscillator. if this bit is set by cpu software, it needs 32 us to ha ve stable output after ihrcoe is enabled. bit 3~2: mcks[1:0], mck source selection. mcks [ 1 :0] mck source selection osc in =12mhz ckmis = [01 ] oscin =11.059mhz ckmis = [01 ] 0 0 oscin 12mhz 11.059mhz 0 1 ckmi x 4 (enckm =1) 24mhz 22.118mhz 1 0 ckmi x 5.33 (enckm =1) 32mhz 29.491mhz 1 1 ckmi x 8 (enckm =1) 48mhz 44.236mhz bit 1~0: osc[1:0], oscin source selection. c kmis [ 1 :0] oscin source selection 0 0 ihrco 0 1 xtal 1 0 ilrco 1 1 ecki, external clock input (p6.0) as oscin. ckcon 3 : clock control register 3 sfr page = p only
megawin mg82fg5b xx data sheet 41 sfr address = 0x41 reset = 0000 - 0010 7 6 5 4 3 2 1 0 0 0 fwkp 0 mckd1 mckd0 mcds 1 mcds0 w w r /w w r/w r/ w r/w r/w auxr0: auxiliary register 0 sfr page = 0~f sfr address = 0xa1 reset = 000 0 - 0000 7 6 5 4 3 2 1 0 p60oc1 p60oc0 p60fd t0xl p4fs1 p4fs0 int1h int0h r/w r/w r/w r/ w r/w r/w r/w r/w bit 7~6: p6.0 function configured control bit 1 and 0. the two bits only act when internal rc oscillator (ihrco or ilrco) is selected for system clock source. in crystal mode, xtal2 and xtal1 are the alternated function of p6.0 and p6.1. in external clock input mode, p6.0 is the dedicated clock input pin . in internal oscillator condition, p6.0 provides the following selections for gpio or clock source generator. when p60oc[1:0 ] index to non - p6.0 gpio function, p6.0 will drive the on - chip rc oscillator (ihrco or ilrco) output to provide the clock source for other devices. p60oc[1:0] p6.0 function i/o mode 00 p60 b y p6m0.0 01 mck/1 b y p6m0.0 10 mck/2 b y p6m0.0 11 mck/ 4 b y p6m0.0 for clock - out on p6.0 function, it is recommended to set p6m0.0 to ? 1 ? which selects p6.0 as push - push output mode. bit 5: p60fd, p6.0 fast driving. 0: p6.0 output with default driving. 1: p6.0 output with fast driving enabled. if p6.0 is configured to clock output, enable this bit when p6.0 output frequency is more than 12mhz at 5v application or more than 6mhz at 3v application.
42 mg82fg5b xx data sheet megawin 9.3. system clock sample code (1 ) required function: switch ihrco from default 1 2mhz to 11.0592 mhz assembly code example: orl ckcon0,#(afs) ; se lect ihrco to output 11. 0592 mhz c code example: ckcon0 |= a fs; // se lect ihrco to output 11. 0592 mhz. (2). required function: switch sysclk to oscin/ 2 (default is oscin/ 1 ) assembly code example: anl ckcon0,#(afs) ; set scks[2:0] = 1 to select oscin / 2 orl ckcon0,#( scks 0 ) ; c code example: ckcon0 &= ~(scks2 | scks1 ); // system clock divider / 2 ckcon0 | = (scks 0 ); // oscin/ 2 // scks[2:0] , system clock divider // 0 | oscin/1 // 1 | oscin/2 // 2 | oscin/4 // 3 | oscin/8 // 4 | oscin/16 // 5 | oscin/32 // 6 | oscin/64 // 7 | oscin/128
megawin mg82fg5b xx data sheet 43 10. watch dog timer (wdt) 10.1. wdt structure the watch - dog timer (wdt) is intended as a recovery method in situations where the cpu may be subjected to software upset. the wdt consists of a 9 - bit free - running cou nter , a 7 - bit prescaler and a control register (wdtcr). figure 10? 1 shows the wdt structure in mg82fg5bxx . w he n wdt is enabled, it derives its time base from the 3 2k hz ilrco. the wdt overflow will set the wdtf on pcon1.0 which can be configured to generate an interrupt by enabled wdtfie (sfie.0) and enabled esf (eie1.3). the overflow can also trigger a system reset when wren (wdtcr.7) is set. t o prevent wdt overflow, software needs to clear it by writing ?1? to the clrw bit (wdtcr.4) before wdt overflows . once the wdt is enabled by setting enw bit, there is no way to disable it except through power - on reset or page- p sfr over - write on enw , which will clear the enw bit. the wdtcr register will keep the previous prog rammed value unchanged after hardware (rst - pin) reset, software reset and wdt reset . wren, nsw and enw are implemented to one - time - enabled function, only writing ? 1 ? valid in general sfr page. page - p sfr access on wdtcr can disable wren, nsw and enw, writ ing ? 0 ? on wdtcr.7~5. please refer section ? 10.3 wdt register ? and section ? 27 page p sfr access ? for more detail information. figure 10? 1 . watch dog timer ps0 1/1 7-bits prescaler 9-bits wdt wdtcr register 1/128 1/64 1/32 1/16 1/8 1/4 1/2 widl ps1 ps2 clrw enw nsw wren pcon0.idl wdt reset pcon0.pd ilrco(32khz) wdtf pcon1.0 sfie.wdtfie eie1.esf wdt interrupt widl wren overflow 10.2. wdt during idle and power down in the idle mode, the widl bit (wdtcr.3) determines whether wdt counts or not. set this bit to let wdt keep counting in the idle mode. if the hardware option nswdt is enabled, the wdt always keeps counting regardless of widl bit. in the power down mode, the il rco won?t stop if the nsw (wdtcr.6) is enabled. the muc enters watch mode. that lets wdt keep counting even in power down mode (watch mode) . after wdt overflows, it will wake up the cpu from interrupt or reset by software configured.
44 mg82fg5b xx data sheet megawin 10.3. wdt register wdtcr: watch - dog - timer control register sfr page = 0~f & p sfr address = 0xe1 por = xxx0 - xxxx (0000 - 0111) 7 6 5 4 3 2 1 0 wren nsw enw clrw widl ps2 ps1 ps0 r/ w r/ w r/ w r/w r /w r /w r /w r /w bit 7: wren, wdt reset enable. the initial value can be changed by hardware option, wreno . 0: the overflow of wdt does not set the wdt reset. t he wdt ov erflow flag, wdtf, may be polled by software or trigger an interrupt. 1: the overflow of wdt will cause a system reset. once wren has been set, it can not be cleared by software in page 0~f. in page p, software can modify it to ? 0 ? or ? 1 ? . bit 6: nsw. non - stopped wdt . the initial value can be changed by hardware option, nswdt. 0: wdt stop counting while the mcu is in power - down mode. 1: wdt always keeps counting while the mcu is in power - down mode (watch mode) or idle mode. once nsw has been set, it can no t be cleared by so ftware in page 0~f . in page p, software can modify it to ? 0 ? or ? 1 ? . bit 5: enw. enable wdt. 0: disable wdt running. this bit is only cleared by por. 1: enable wdt while it is set. once enw has been set, it can not be cleared by software in page 0~f . in page p, software can modify it as ? 0 ? or ? 1 ? . bit 4: clrw. wdt clear bit. 0: writing ? 0 ? to this bit is no operation in wdt. 1: writing ?1? to this bit will clear the 9 - bit wdt counter to 000h. note this bit has no need to be cleared by w riting ?0? . bit 3: widl. wdt idle control. 0: wdt stops counting while the mcu is in idle mode. 1: wdt keeps counting while the mcu is in idle mode . bit 2~0: ps2 ~ ps0, select prescaler output for wdt time base input. ps[ 2 :0] prescaler value wdt period 0 0 0 1 15 ms 0 0 1 2 31 ms 0 1 0 4 62 ms 0 1 1 8 124 ms 1 0 0 16 248 ms 1 0 1 32 496 ms 1 1 0 64 992 ms 1 1 1 128 1.984 s pcon1: power control register 1 sfr page = 0~f & p sfr address = 0x97 por = 0010 - x000 7 6 5 4 3 2 1 0 s wrf exrf mcdf rtcf -- bof1 bof0 wdtf r/w r/w r/ w r/ w w r /w r /w r/w bit 1: wdtf, wdt overflow flag. 0: this bit must be cleared by software writing ? 1 ? on it. software writing ? :0 ? is no operation. 1: this bit is only set by hardware when wdt overflows. writing ? 1 ? on this bit will clear wdtf.
megawin mg82fg5b xx data sheet 45 10.4. wdt hardware option in addition to being initialized by software, the wdtcr register can also be automatically initialized at power - up by the hardware options wreno, nswdt, hwenw, hwwidl and hwps[2:0], which sho uld be programmed by a universal writer or programmer, as described below. if hwenw is programmed to ?enabled?, then hardware will automatically do the following initialization for the wdtcr register at power - up: (1) set enw bit, (2) load wreno into wren bit, (3) load nswdt into nsw bit, (4) load hwwidl into widl bit, and ( 5 ) load hwps[2:0] into ps[2:0] bits. if both of hwenw and wdsfwp are programmed to ? enabled ? , hardware still initializes the wdtcr register content by wdt hardware option at power - up. t hen, any cpu writing on wdtcr bits will be inhibited except writing ? 1 ? on wdtcr.4 (clrw), clear wdt, even though access through page - p sfr mechanism. w reno : ?: e nabled . set wdtcr.wren to enable a system reset function by wdtf. ? : d isabled . clear wdtcr. wren to disable the system reset function by wdtf. nswdt : non - stopped wdt ?: e nable d. set wdtcr.nsw to enable the wdt running in power down mode (watch mode) . ? : d isable d. clear wdtcr.nsw to disable the wdt running in power down mode (d isable w atch mode ) . hwenw : hardware loaded for ? enw ? of wdtcr. ?: e nable d. e nable wdt and load the content of wreno, nswdt, hwwidl and hwps2 ~ 0 to wdtcr after power - on . ? : d isable d. wdt is not enabled automatically after power - on. hwwidl, hwps2, hwps1, hwps0 : when hwenw is enabled , the content on these four fused bits will be loaded to wdtcr sfr after power - on. wdsfwp : ?: e nable d. the wdt sfr s, wren, nsw, widl, ps2, ps1 and ps0 in wdtcr , will be write - protected. ? : d isable d. the wdt sfr s, wren, nsw, widl, ps2, ps1 and ps0 in wdtcr , are free for writing of software.
46 mg82fg5b xx data sheet megawin 10.5. wdt sample code (1 ) required function: enable wdt and select wdt period to 248ms assembly code example: or l pcon1,#(wdtf) ; clear wdtf flag (write ?1 ?) mov wdtcr,#(enw | clrw | ps2) ; enable wdt counter and set wdt period to 248 ms c code example: pcon1 | = wdtf; // clear wdt flag (write ?1 ?) wdtcr = (enw | clrw | ps2 ) ; // enable wdt count er and set wdt period to 248 ms // ps[2:0] | wdt period selection // 0 | 15ms // 1 | 31ms // 2 | 62ms // 3 | 124ms // 4 | 248ms // 5 | 496ms / / 6 | 992ms // 7 | 1.984s ( 2 ) required function: how to disable wdt assembly code example: mov ifd,wdtcr ; read w d t cr data anl ifd,#~(enw) ; clear enw to disable wdt mov ifadrl,#(wdtcr_p) ; index page -p address to wdtcr_p call _page_p_sfr_write ; write data to wdtcr c code example: ifd = wdtcr; // read wdtcr data ifd &= ~enw; // clear enw to disable wdt ifadrl = wdtcr_p; // index page -p address to wdtcr_p page_p_sfr_write(); // write data to wdtc r ( 3 ). required function: enable wdt re set function and select wdt period to 62ms assembly code example: or l pcon1,#(wdtf) ; clear wdtf flag (write ?1 ?) mov wdtcr,#(wren | clrw | ps 1 ) ; enable wdt reset function and set wdt period to 62 ms orl wdtcr,# (enw) ; enable wdt counter, wdt running c code example: pcon1 | = wdtf; // clear wdtf flag (write ?1 ?) wdtcr = wren | clrw | ps 1 ; // enable wdt reset function and set wdt period to 62ms wdt cr |= enw; // enable w dt counter , wdt running. ( 4 ). required function: enable protected write for wdtcr assembly code example: or l pcon1,#(wdtf) ; clear wdtf flag (write ?1 ?) mov wdtcr,#(enw | cl rw | ps2) ; enable wdt counter and set wdt period to 248 ms mov ifadrl,#(spcon0) ; index page -p address to spcon0 call _page_p_sfr_read ; read spcon0 data
megawin mg82fg5b xx data sheet 47 orl ifd,#(wrctl) ; enable pro t ected write for wdtcr call _page_p_sfr_write ; write data to spcon0 mov ifd,wdtcr ; read wdt cr data orl ifd,#(clrw) ; enable clrw mov ifadrl,#(wdtcr_p) ; in dex page -p address to wdtcr_p call _page_p_sfr_write ; write data to wdtcr to clear wdt counter c code example: pcon1 | = wdtf; // clear wdtf flag (write ?1 ?) wdtcr = enw | clrw | ps2; // enable wdt counter and set wdt period to 24 8 ms ifadrl = spcon0; // index page -p address to spcon0 page_p_sfr_read(); // read spcon0 data ifd |= wrctl; // enable prot ected write for wdtcr page_p_sfr_write(); // write data to spcon0 ifd = wdtcr; // read wdtcr data ifd |= clrw; // enable clrw ifadrl = wdtcr_p; // i ndex page -p address to wdtcr_p page_p_sfr_write(); // write data to wdtcr to clear wdt counter
48 mg82fg5b xx data sheet megawin 11. real - time - clock(rtc)/system - timer 11.1. r t c structure the mg82fg5bxx has a simple real - time clock that allows a user to continue ru nning an accurate timer while the rest of the device is powered - down. the real - time clock can be a wake - up or an interrupt source. the real - time clock is a 21- bit up counter comprised of a 14/15 - bit prescaler and a 6 - bit loadable up counter. when it overfl ows , the counter will be reloaded again and the rtcf flag will be set. the clock source for this prescaler can be e ither the system clock (sysclk) or the xtal oscillator, provided that the xtal oscilla tor is not being used as the system clock. figure 11? 1 shows the rtc structure in mg82fg5bxx . the 32.768khz crystal for the rtc module input will provide a programmable overflow period for 0.5s to 64s. the counter also provides a timer function with the clock derived from sysclk/12 or sysclk/2^15 for a short timer function or a long system timer function. the maximum overflow period for the system timer function is sysclk/2^21. if the xtal oscillator is used as the system clock, then the rtc still use s p6.0 input as i ts clock source. only power - on reset will reset the real - time clock and its associated sfrs to the default state. figure 11? 1 . real - time - clock counter rtc prescaler rtctm register rtcct[5:0] rtccs[1:0] sfie.rtcfie eie1.esf rtc interrupt 0 1 2 3 xtal2/ecki (p 6.0) (32.768 khz) sysclk rtcct[5:0] rtcrl[5:0] overflow reload rtcf pcon1.4 p6.0/2^14 ( 0.5s) p6.0/2^15 ( 1.0s) sysclk/2^15 rtccs[1:0] rtccr register rtcoe rtce rtcrl[5:0] 6-bit counter sysclk/12 rtcko 0 1 sfr p4.5 toggle q 00: p6.0/2 ^14 (0.5s) 01: p6.0/2 ^15 (1s) 10: sysclk/12 11: sysclk/2^15
megawin mg82fg5b xx data sheet 49 11.2. rtc register rtccr: real - time - clock control reg ister sfr page = normal & page p sfr address = 0xbe por = 0011 - 1111 7 6 5 4 3 2 1 0 rtce rtcoe rtcrl.5 rtcrl.4 rtcrl.3 rtcrl.2 rtcrl.1 rtcrl.0 r/w r/ w r/w r/w r/w r/w r/w r/w bit 7: rtce, rtc enable. 0: stop rtc counter, rtcct. 1: enable rtc counter and set rtcf when rtcct overflows. when rtce is set, cpu can not access rtctm. rtctm must be accessed in rtce cleared. bit 6: rtcoe, rtc output enabled. the frequency of rtcko is (rtc overflow rate)/2. 0: disable the rtcko output. 1: enable the rt cko out put on p4.5. bit 5~0: rtcrl[5:0], rtc counter reload value register. this register is accessed by cpu and the content in the register is reloaded to rtcct when rtcct overflows. rtctm: real - time - clock timer register sfr page = normal sfr address = 0xb6 por = 0111 - 1111 7 6 5 4 3 2 1 0 rtccs.1 rtccs.0 rtcct.5 rtcct.4 rtcct.3 rtcct.2 rtcct.1 rtcct.0 r/w r/ w r/w r/w r/w r/w r/w r/w bit 7 ~6 : rtccs .1~0 , rtc clock selection. default is ?01?. rtcc s[ 1 :0] clock source rtc interrupt duration min. step 0 0 p 6 .0/2^14 0.5s ~ 32s when p 6 .0 = 32768hz 0.5s 0 1 p 6 .0/2^15 1s ~ 64s when p 6 .0 = 32768hz 1s 1 0 sysclk / 1 2 1 us ~ 64 us when sysclk = 12mh z 1 us 1 1 sysclk/2^15 2.73ms ~ 174. 72 ms when sysclk = 12mhz 2.73ms bit 5~0: rtcct[5:0], rtc counter register. it i s a counter for rtc function or system timer function by different clock source selection on rtccs[1:0]. when the counter overflows, it sets the rtcf flag which shares the system flag interrupt when rtcfie is enabled. the maximum rtc overflow period is 64 seconds. pcon1: power control register 1 sfr page = 0~f & p sfr address = 0x97 por = 0 0 00- x000 7 6 5 4 3 2 1 0 swrf exr f mcdf rtcf -- bof1 bof0 wdtf r/w r/w r/w r /w w r /w r /w r/w bit 4: rtcf, rtc overflow flag. 0: this bit must be cleared by soft ware writing ? 1 ? on it. software writing ? :0 ? is no operation. 1: this bit is only set by hardware when rtcct overflows. writing ? 1 ? on this bit will clear rtcf.
50 mg82fg5b xx data sheet megawin sfie: system flag interrupt enable register sfr page = 0~f sfr address = 0x8e por = 0 11 0 - x000 7 6 5 4 3 2 1 0 sidfie mcdre mcdfie rtcfie -- bof1ie bof0ie wdtfie r/w r/w r/w r/w w r/w r/ w r/w bit 4: rtcfie, enable rtcf (pcon1.4) interrupt. 0: disable rtcf interrupt. 1: enable rtcf interrupt. if enabled, rtcf will wake up cpu in idle mode or power - down mode.
megawin mg82fg5b xx data sheet 51 11.3. rtc sample code ( 1 ). required function: enable xtal 32.768khz oscillation for rtc application assembly code example: mov ifadrl,#(ckcon2) ; index page -p address to ckcon2 call _page_p_sfr_read ; read ck c on2 data anl ifd,#~(xtgs1 | xtgs0) ; set xtal to low gain for 32.768khz orl ifd,#(xtale) ; enable xtal oscillating call _page_p_sfr_write ; write data to ck c on2 check_xtor_0: ; check xtal oscillating ready mov a, ckcon 1 jnb acc. 7 ,check_xtor_0 ; waiting for xtor( ckcon 1. 7 ) true c code example: ifadrl = ckcon2; // index page -p addres s to ckcon2 page_p_sfr_read(); // read ckcon2 data ifd &= ~( xtgs1 | xtgs0 ); // set xtal to low gain for 32.768khz ifd |= xtale; // enable xtal oscillating page_p_sfr_write() ; // write data to ckcon2 while( ckcon 1&xtor == 0x00 ); // check xtal oscillating ready // waiting for xtor( ckcon 1. 7 ) true ( 2 ) required function: enable system timer interrupt with 174.72ms duration (when sysclk = ihrco = 12mhz in default) assembly code example: org 000 5 bh systemflag_isr : or l pcon1,#(rtcf) ; clear rtc flag (write ?1 ?) reti main: or l pcon1,#(rt cf) ; clear rtc flag (write ?1 ?) mov rtctm,#(rtccs1 | rtccs0) ; select sysclk/2^15 for rtc counter clock source ; rtcct[5:0 ] = 0 for 174.72ms duration mov rtccr,#(rtce) ; set rtc reload count , rtcrl[5:0] = 0 for 174.72ms duration ; enable rtc counter orl sfie ,#( r tcf ie ) ; enable rtc interrupt orl eie1 ,#( es f) ; enable systemflag interrupt setb ea ; enable global interrupt c code example: void system flag _ isr (void) interrupt 11 { pcon1 | = rtcf; // clear rtc flag (write ? 1 ?) } viod main (void) { pcon 1 | = rtcf; // clear rtc flag (write ? 1 ?) rtctm = rtccs1 | rtccs0; // select sysclk/2^15 for rtc counter clock source // rtcct[5:0 ] = 0 for 174.72ms duration rtccr = rtce; // set rtc reload count , rtcrl[5:0] = 0 for 174.72ms duration // enable rtc counter
52 mg82fg5b xx data sheet megawin sfie |= rtcfie; // enable rtc interrupt eie1 |= esf; // enable systemflag interrupt ea = 1; // enable global interrupt } ( 3 ). required function: enable rtcko to output sysclk/12/2 assembly code example: orl p4 m0,#20h ; set rtcko ( p4 . 5) to push - pull output mode mov rtctm,# 0bf h ; rtc clock select sysclk/12 and set rtcct [5:0] = 3fh mov rtccr,# 03f h ; set rtcrl[5:0] = 3fh orl rtccr,#(rtce|rtcoe) ; enable r tc counter and rtcko output c code example: p4 m0 | = 0x20; // set rtcko ( p4 . 5) to push - pull output mode rtctm = 0x bf ; // rtc clock select sysclk/12 and set rtcct [5:0] = 3fh rtccr | = 0x3f; / / set rtcrl[5:0] = 3fh rtccr | = (rtce | rtcoe); / / enable rtc counter and rtcko output
megawin mg82fg5b xx data sheet 53 12. system reset during reset, all i/o registers are set to their initial values, and the program starts execution from the reset vector, 0000h , or isp start address by or setting . the mg82fg5bxx has seven sources of reset: power - on reset, external reset , software reset, illegal address reset, brown - out reset 0, brown - out reset 1 and wdt reset. figure 12? 1 shows the system reset source in mg82fg5bxx . the following sections describe the reset happened source and corresponding control registers and indicating flags. 12.1. reset source figure 12? 1 presents the reset systems in the mg82fg5bxx and all of its reset sources. figure 12? 1 . system reset source internal system reset (sysrst) external reset wdt reset software reset power-on reset illegal addr reset swrf exrf pof0 pcon2.bo0re bod1 triggered pcon2.bo1re wdtcr.wren brown-out reset 1 brown-out reset 0 wdt overflow bod0 triggered 12.2. p ower - on reset power - on reset (por) is used to internally reset the cpu during power - up. th e cpu will keep in reset state and will n ot start to work until the vdd power rises above the voltage of power - on reset . and, the reset state is activated again whenever the vdd power falls below the por voltage . d uring a po wer cycle, vdd must fall below t he por voltage before p o wer is reapplied in order to ensure a power - on reset pcon 0 : power control register 0 sfr page = 0~f & p sfr address = 0x 87 por = 0001 - 0000, reset = 000x - 0000 7 6 5 4 3 2 1 0 smod 1 smod0 gf pof0 gf1 gf0 pd idl r/w r/w r/w r/w r /w r/w r/w r/w bit 4: pof 0, power - on flag 0 . 0: the flag must be cleared by software to recognize next reset type . 1: s et by hardware when v dd rises from 0 to its nominal voltage. pof0 can also be set by software. the power - on flag, pof 0, is set to ?1? by hardware du ring power up or when vdd power drops below th e por voltage. it can be clear by firmware and is not affected by any warm reset such as external reset, brown - out reset, software reset (ispcr.5) and wdt reset. it helps users to check if the run ning of the cpu begins from power up or not . note that the pof0 must be cleared by firmware .
54 mg82fg5b xx data sheet megawin 12.3. external reset a reset is accomplished by holding the r e s e t pin high for at least 2 4 oscillator periods while the oscillator is running. to e nsure a reliable po wer - up reset, the hardware reset from rst pin is necessary. pcon1: power control register 1 sfr page = 0~f & p sfr address = 0x97 por = 000 0 - x000 7 6 5 4 3 2 1 0 swrf exrf mcdf rtcf -- bof1 bof0 wdtf r/w r/w r/ w r/ w w r/w r/w r/w bit 6: exrf, exter nal reset flag. 0: this bit must be cleared by software writing ? 1 ? on it. software writing ? :0 ? is no operation. 1: this bit is only set by hardware if an external reset occu rs. writing ? 1 ? on this bit will clear exrf. 12.4. software reset software can trigg er the cpu to restart by software reset, writing ? 1 ? on swrst (ispcr.5), and set the swrf flag (pcon1.7). swbs decides the cpu is boot from isp or ap region after the reset action ispcr : isp control register sfr page = 0~f sfr address = 0xe7 reset = 00 00- x000 7 6 5 4 3 2 1 0 ispen swbs swrst cfail -- datm2 datm1 datm0 r/w r/w r/w r/w w w w w b it 6: swbs, software boot selection control. 0 : boot from ap- memor y after reset . 1 : boot from isp memory after reset . b it 5: swrst, software reset trigger co ntrol. 0 : write ? 0 ? is n o operation 1 : write ? 1 ? to g enerate software system reset. it will be cleared by hardware automatically. pcon1: power control register 1 sfr page = 0~f & p sfr address = 0x97 por = 000 0 - x000 7 6 5 4 3 2 1 0 swrf exrf mcdf rtc f -- bof1 bof0 wdtf r/w r/w r/ w r/ w w r/w r/w r/w bit 7: swrf, software reset flag. 0: this bit must be cleared by software writing ? 1 ? on it. software writing ? 0 ? is no operation. 1: this bit is only set by hard ware if a software reset occurs. writing ? 1 ? on this bit will clear swrf.
megawin mg82fg5b xx data sheet 55 12.5. brown - out reset in mg82fg5bxx , there are two brown - out detectors (bod0 & bod1) to monitor vdd power. bod0 services the fixed detection level at vdd= 1.7 v. bod1 detects the vdd level by software selecting 4.2v, 3.7v, 2.4v or 2.0v. if vdd power drops below bod0 or bod1 monitor level. associated flag, bof0 and bof1, is set. if bo0re (pcon2.1) is enabled, bof0 indicates a bod0 reset occurred. if bo1re (pcon2.3) is enabled, bof1 indicates a bod1 reset occurred . pcon1: power c ontrol register 1 sfr page = 0~f & p sfr address = 0x97 por = 00 0 0 - x000 7 6 5 4 3 2 1 0 swrf exrf mcdf rtcf -- bof1 bof0 wdtf r/w r/w r/ w r/ w w r/w r/w r/w bit 2: bof1, bof1 (reset) flag. 0: this bit must be cleared by software writing ? 1 ? on it. so ftware writing ? :0 ? is no operation. 1: this bit is only set by hardware when vdd meets bod1 monitored level. writing ? 1 ? on this bit will clear bof1. if bo1re (pcon2.3) is enabled, bof1 indicates a bod1 reset occurred. bit 1: bof0, bof0 (reset) flag. 0: this bit must be cleared by software writing ? 1 ? on it. software writing ? :0 ? is no operation. 1: this bit is only set by hardware when vdd meets bod0 monitored level. writing ? 1 ? on this bit will clear bof0. if bo0re (pcon2.1) is enabled, bof0 indicates a bod0 reset occurred. 12.6. wdt reset when wdt is enabled to start the counter, wdtf will be set by wdt overflow. if wren (wdtcr.7) is enabled, the wdt overflow will trigger a system reset that causes cpu to restart. software can read the wdtf to recognize th e wdt reset occurred. pcon1: power control register 1 sfr page = 0~f & p sfr address = 0x97 por = 0010 - x000 7 6 5 4 3 2 1 0 swrf exrf mcdf rtcf -- bof1 bof0 wdtf r/w r/w r/ w r/ w w r/w r/w r/w bit 0: wdtf, wdt overflow/reset flag. 0: this bit must b e cleared by software writing ? 1 ? on it. software writing ? :0 ? is no operation. 1: this bit is only set by hardware when wdt overflows. writing ? 1 ? on this bit will clear wdtf. if wren (wdtcr.7) is set, wdtf indicates a wdt reset occurred. 12.7. illegal addres s reset in mg82fg5bxx , if software program runs to illegal address such as over program rom limitation, it triggers a reset to cpu.
56 mg82fg5b xx data sheet megawin 12.8. reset sample code (1 ) required function: trigger a software reset assembly code example: orl ispcr,#swrst ; trigger software reset c code example: ispcr | = swrst; // trigger software reset (2). required function: enable bod0 reset assembly code example: mov ifadrl,#pcon2 ; index page - p addr ess to pcon2 call _page_p_sfr_read ; read p con 2 data orl ifd,#bo0 re ; enable bod0 reset function call _page_p_sfr_write ; write data to p con 2 c code example: ifadrl = p con2; // index page - p address to pcon2 page_p_sfr_read(); // read p con 2 data ifd | = bo0re ; // enable bod0 reset function page_p_sfr_write(); // write data to pcon2
megawin mg82fg5b xx data sheet 57 13. power management the mg82fg5bxx supports two power monitor modules, brown - out detector 0 (bod0) and brown - out detector 1 (bod1), and 6 power - reducing modes: idle mode, power - down mode, slow mode, sub - clock mode, watch mode and monitor mode . bod0 and bod1 report the chip power status on the flags, bof0 and bof1, which provide the capability to interrupt cpu or to reset cpu by software configured. the six power - reducing modes provide the different power - saving scheme for chip application . the se modes are accessed through the ckcon0, ckcon2, pcon0, pcon1, pcon2, pcon3 and wdtcr register. 13.1. brown - out detector in mg82fg5bxx , there are two brown - out detectors (bod0 & bod1) to monitor vdd power. figure 13 ? 1 shows the function al diagram of bod0 and bod1. bod0 services the fixed detection level at vdd=2.2v and bod1 detects the software selection levels (4.2v/3.7v/2.4v/2.0v) on vdd. associated flag, bof0 (pcon1.1), is set when bod0 meets the detection level. i f both of esf (eie1.3) and bof0ie (sfie.1) are enabled, a set bof0 will generate a system flag interrupt. it can interrupt cpu either cpu in normal mode or idle mode. the bod1 has the same flag function, bof1, and same interrupt function . the bod1 interrup t also wakes up cpu in power down mode if awbod1 (pcon 2 . 7 ) is enabled. if bo0re (pcon2.1) is enabled, the bod0 event will trigger a system reset and set bof0 to indicate a bod0 reset occurred. the bod0 reset restart the cpu either cpu in normal mode or id le mode. bod1 also has the same reset capability with associated control bit, bo1re (pcon2.3). the bod1 reset also restart cpu in power down mode if awbod1 (pcon 2 . 7 ) is enabled in bod1 reset operation. to reduce power consumption, software may clear ebod1 (pcon2.2) to disable bod1 if the bod1 is not applied in user application . figure 13? 1 . brown - out detector 0/1 1 . 7 v vdd voltage comparator + - 1 load bof0 bod0 interrupt bod0 reset pcon0.pd enable (pcon1.1) bof0ie (sfie.1) esf (eie1.3) bo0re (pcon2.1) vdd voltage comparator + - 1 load bof1 bod1 interrupt bod1 reset pcon0.pd enable (pcon1.2) bof1ie (sfie.2) esf (eie1.3) bo1re (pcon2.3) awbod1 (pcon2.7) 0 1 2 3 4.2v 3.7v 2.4v 2.0v 00: 2.0v 01: 2.4v 10: 3.7v 11: 4.2v bo1s1,0 (pcon2.5~4)
58 mg82fg5b xx data sheet megawin 13.2. power saving mode 13.2.1. slow mode the alternative to save the operating power is to slow the mcu?s operating speed by programming sck s 2~sck s 0 bits (in ckcon0 register, see section ? 9 system clock ? ) to a non - 0/0/0 value. the user should examine which program segm ents are suitable for lower operating speed. in principle, the lower operating speed should not affect the system?s normal function. then, restore its normal speed in the other program segments. 13.2.2. sub - clock mode the alternative to slow down the mcu?s operat ing speed by programming oscs1~0 can select the ilrco for system clock. t he 32khz ilrco provides the mcu to operates in an ultra low speed and low power operation. additional programming sck s 2~sck s 0 bits (in ckcon0 register, see section ? 9 system clock ? ) , t he user could put the mcu speed down to 250hz slowest . 13.2.3. rtc mode the mg82fg5bxx has a simple r tc module that allows a user to continue running an accurate timer while t he rest of the device is powered - down. in rtc mode, t he rtc module behaves a ? c lock? function and can be a wake - up source from chip power down by rtc overflow rate. please refer section ? 11 real - time - clock(rtc)/system - timer ? for more detail information. 13.2.4. watch mode if watch - dog - timer is enabled and nsw is set, watch - dog - timer will keep running in power down mode to support an auto - wakeup function , which named watch mode in mg82fg5bxx . wh en wdt overflows, set wdtf and wakeup cpu from interrupt or system reset by software configured. the maximum wakeup period is about 2 seconds that is defined by wdt pre - scaler. please refer section ? 10 watch dog timer (wdt) ? and section ? 15 interrupt ? for more detail information. 13.2.5. monitor mode if awbod1 (pcon3.3) is set, bod1 will keep vdd monitor in power down mode. it is the monitor mode in mg82fg5bxx . when bod1 meets the detection level, set bof1 and wakeup cpu from interrupt or system reset by software configured. please refer section ? 13.1 brown - out detector ? and section ? 15 interrupt ? for more detail information. 13.2.6. idle mode setting the idl bit in pcon enters idl e mode. idle mode halts the internal cpu clock. the cpu state is preserved in its entirety, including the ram, stack pointer, program counter, program status word, and accumulator. the port pins hold the logical states they had at the time that idle was ac tivated. idle mode leaves the peripherals running in order to allow them to wake up the cpu when an interrupt is generated. timer 0, timer 1 , timer 2, nint0~nint3, uart0, uart 1, spi, twi 0 , twi1, kbi, adc, sid, rtc, bod0 and bod1 will continue to function d uring idle mode. pca timer and wdt are conditional enabled during idle mode to wake up cpu . any enabled interrupt source or reset may terminate idle mode. when exiting idle mode with an interrupt, the interrupt will immediately be serviced, and following r eti, the next instruction to be executed will be the one following the instruction that put the device into idle. the adc input channel s must be set to ? analog input only ? in p1aio sfr when mcu is in idle mode or power - down mode. 13.2.7. power - down mode setting the pd bit in pcon 0 enters power - down mode. power - down mode stops the oscillator and powers down the flash memory in order to minimize power consumption. only the power - on circuitry will continue to draw power during power - down. during power - down the power supply voltage may be reduced to the ram keep - alive voltage. the ram contents will be retained; however, the sfr contents are not guaranteed once vdd has been reduced. power - down may be exit by external reset, power - on reset, enabled external interrupts , enabled kbi, enabled rtc (rtc mode) , enabled bod1 (monitor mode) or enabled non - stop wdt (watch mode) . the user should not attempt to enter (or re - enter) the power - down mode for a minimum of 4 s until after one of the following conditions has occurred: s tart of code execution (after any type of reset), or exit from power - down mode. to ensure minimum power consumption in power down mode, software must confirm all i/o not in floating state, including the port i/os un - appearance on package pins. for example, p 2 . 5 and p 2 . 7 are not bonding - out in
megawin mg82fg5b xx data sheet 59 mg82fg5b32 a s2 8 ( sop2 8) package pins. software may configure p 2.5 /p 2.7 corresponding bit sfr to ? 0 ? (output low) to avoid pin floating in power - down mode. figure 13? 2 shows the wakeup mechanism of power - down mode in mg82fg5bxx . figure 13? 2 . wakeup structure of power down mode ie 3 xicon . int 3 h 0 1 xicon . it 3 = 0 nint 3 input nint 2 input ie 2 0 1 xicon . int 2 h xicon . it 2 = 0 ie 1 auxr 0 . int 1 h 0 1 tcon . it 1 = 0 nint 1 input nint 0 input ie 0 0 1 auxr 0 . int 0 h tcon . it 0 = 0 ie . ex 0 ie . ex 1 xicon . ex 2 xicon . ex 3 force to level - sensitive in pd force to level - sensitive in pd force to level - sensitive in pd force to level - sensitive in pd kbif eie 1 . ekb exf 2 ie . et 2 rxd 1 pin 0 1 scon 1 . rb 81 s 1 con . ren 1 s 1 cfg . s 1 tme ri 1 es 1 timer 2 external input wakeup s 1 timer external input wakeup rtc wakeup keypad wakeup nint 3 wakeup nint 2 wakeup nint 1 wakeup nint 0 wakeup wdtf eie 1 . esf sfie . wdtfie overflow wdtcr . nsw wdt wakeup wdtcr . wren external reset reset wakeup wdt reset event or clear pcon 0 . pd & wakeup cpu wdt bof 0 eie 1 . esf sfie . bof 0 ie ilrco bod 0 pcon 2 . awbod 0 bof 1 eie 1 . esf sfie . bof 1 ie bod 1 pcon 2 . awbod 1 pcon 2 . bo 0 re pcon 2 . bo 1 re bod 0 wakeup bod 1 wakeup pcon 0 . pd pcon 0 . pd pcon 0 . pd pcon 2 . ebod 0 pcon 2 . ebod 1 wdtcr . enw en en en bod 0 reset bod 1 reset rtcf eie 1 . esf sfie . rtcfie
60 mg82fg5b xx data sheet megawin 13.2.8. interrupt recovery from power - down four external interrupts may be configured to terminate power - do wn mode. external interrupts n int0 , n int1 , nint2 and nint3 may be used to exit power - down. to wake up by external interrupt n int0 , n int1 , nint2 or nint3, the interrupt must be enabled and configured for level - sensitive oper ation. if the enabled external in terrupts are configured to edge - sensitive operation (falling or rising), they will be forced to level - sensitive operation (low level or high level) by hardware in power - down mode. when terminating power - down by an interrupt, the wake up period is internal ly timed. at the falling edge on the interrupt pin, power - down is exited, the oscillator is restarted, and an internal timer begins counting. the internal clock will not be allowed to propagate and the cpu will not resume execution until after the timer ha s reached internal counte r full . after the timeout period , the interrupt service routine will begin. to prevent the interrupt from re - triggering, the isr should disable the interrupt before returning. the interrupt pin should be held low until the device h as timed out and begun executing. 13.2.9. reset recovery from power - down wakeup from power - down through an external reset is similar to the interrupt. at the rising edge of rst, power - down is exited, the oscillator is restarted, and an internal timer begins coun ting. the internal clock will not be allowed to propagate to the cpu until after the timer has reached internal counte r full . the rst pin must be held high for longer than the timeout period to ensure that the device is reset properly. the device will begi n executing once rst is brought low. it should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. on - chip hardware inhibits access to internal ram in this event, but access to the port pins is not inhibited. to eliminate the possibility of an unexpected write to a port pin when idle is terminated by reset, the instruction following the one that invokes i dle should not be one that writes to a port pin or to external memory. 13.2.10. kbi wakeup recovery from power - down the keypad interrupt of mg82fg5bxx , p2.7 ~ p2.0 have wakeup cpu capability that are enabled by the control registers in kbi module. or software can configure the p1kbih on auxr1.7 to swap high nibble kbi function on port 1 and configure the p3kbil on auxr1.6 to swap low nibble kbi function on port 3. please refer section ? 28 auxiliary sfrs ? for more detailed auxr1 information. wakeup from power - down through an enabled wakeup kbi is same to the interrupt. at the matched condition of enabled kbi pattern and enabled kbi interrupt (eie1.5, ekb) , power - down is exited, t he oscillator is restarted, and an internal timer begins counting. the internal clock will not be allowed to propagate to the cpu until after the timer has reached internal counte r full . after the timeout period , cpu will meet a kbi interrupt and execute t he interrupt service routine.
megawin mg82fg5b xx data sheet 61 13.3. power control register pcon 0 : power control register 0 sfr page = 0~f & p sfr address = 0x87 por = 0001 - 0000, reset = 000 x - 0000 7 6 5 4 3 2 1 0 smod 1 smod0 gf pof 0 gf1 gf0 pd idl r/w r/w r/w r/w r/w r/w r/w r/w b it 4 : pof0 , power - on flag 0. 0: this bit must be cleared by software writing ? 0 ? to it . 1: this bit is set by hardware if a power - on reset occurs. bit 1: pd, power - down control bit. 0: this bit could be cleared by cpu or any exited power - down event. 1: sett ing this bit activates power down operation. bit 0: idl, idle mode control bit. 0: this bit could be cleared by cpu or any exited idle mode event. 1: setting this bit activates idle mode operation . pcon1: power control register 1 sfr page = 0~f & p sfr address = 0x97 por = 0 0 10- x000 7 6 5 4 3 2 1 0 swrf exr f mcdf rtcf -- bof1 bof0 wdtf r/w r/w r/ w r/ w w r /w r /w r/w bit 7: swrf, software reset flag. 0: this bit must be cleared by software writing ? 1 ? to it. 1: this bit is set by hardware if a softw are reset occurs. bit 6: exrf , external reset flag . 0: this bit must be cleared by software writing ? 1 ? to it . 1: this bit is set by hardware if an external reset occurs. bit 5: mcdf. (under verify) bit 4: rtcf, rtc overflow flag. 0: this bit must be cl eared by software writing ? 1 ? on it. software writing ? :0 ? is no operation. 1: this bit is only set by hardware when rtcct overflows. writing ? 1 ? on this bit will clear rtcf. bit 3: reserved. software must write ? 0 ? on this bit when pcon1 is written. bit 2: bof1, brown - out detection flag 1. 0: this bit must be cleared by software writing ? 1 ? to it . 1: this bit is set by hardware if the operating voltage matches the detection level of brown - out detector 1 (4.2v/3.7/2.4/2.0). bit 1: bof0, brown - out detecti on flag 0. 0: this bit must be cleared by software writing ? 1 ? to it . 1: this bit is set by hardware if the operating voltage matches the detection level of brown - out detector 0 (2.2v). bit 0: wdtf, wdt overflow flag. 0: this bit must be cleared by softwa re writing ? 1 ? to it . 1: this bit is set by hardware if a wdt overflow occurs.
62 mg82fg5b xx data sheet megawin pcon2: power control register 2 sfr page = p only sfr address = 0x44 por = 0 0 11- 0101 7 6 5 4 3 2 1 0 awbod1 0 bo1s1 bo1s0 bo1re ebod1 bo0re 1 r/ w w r/ w r/w r/w r/w r/w w bit 7: awbod1, awaked bod1 in pd mode. 0: bod1 is disabled in power - down mode. 1: bod1 keeps operation in power - down mode. bit 6: reserved. software must write ? 0 ? on this bit when pcon 2 is written. bit 5~4: bo1s[1:0]. brown - out detector 1 monitored l evel selection. bo1s [ 1 :0] bod1 detecting level 0 0 2.0v 0 1 2.4v 1 0 3.7v 1 1 4.2v bit 3: bo1re, bod1 reset enabled. 0: disable bod1 to trigger a system reset when bof1 is set. 1: enable bod1 to trigger a system reset when bof1 is set. bit 2: eb od1, enable bod1 that monitors vdd power dropped at a bo1s1~0 specified voltage level. 0: disable bod1 to slow down the chip power consumption. 1: enable bod1 to monitor vdd power dropped. bit 1: bo0re, bod0 reset enabled. 0: disable bod0 to trigger a sys tem reset when bof0 is set. 1: enable bod0 to trigger a system reset when bof0 is set (vdd meets 2.2v). bit 0: reserved. software must w rite ? 1 ? on t his bit when pcon2 is written.
megawin mg82fg5b xx data sheet 63 13.4. power control sample code (1 ) required function: select slow mode with oscin/128 (default is oscin) assembly code example: orl ckcon0,#(scks0 | scks1 | scks2) ; oscin /128 c code example: ckcon0 | = (scks2 | scks1 | scks0); // select s ystem clock divider to oscin / 128 . ( 2 ) required function: select sub - clock mode with oscin ( oscin=32khz) assembly code example: mov ifadrl,#ckcon2 ; index page -p address to ckcon2 call _page_p_sfr_read ; read ckcon2 data anl ifd,#~(oscs1|oscs0) ; switch oscin s ource to ilrco orl ifd,#oscs1 call _page_p_sfr_write ; write data to ckcon2 anl ifd,#~(ihrcoe|xtale) ; d isable ihrco & xtal call _page_p_sfr_write ; write data to ckcon2 mov a,ckco n0 ; s elect s ystem clock = oscin anl a,#~(scks2|scks1|scks0) orl a,#scks0 mov ckcon0,a c code example: ifadrl = ckcon2; // index page - p address to ckcon2 page_p_sfr_read(); // read ck con 2 data ifd & = ~(oscs1 | oscs0); // switch oscin source to ilrco ifd | = oscs1; page_p_sfr_write(); // write data to ckcon2 ifd = ifd & ~(ihrcoe|xtale); // disable i hrco & xtal page_p_sfr_write(); // write data to ckcon2 acc = ckcon0; // s elect s ystem clock = oscin acc & = ~(scks2 | scks1 | scks0); acc | = scks0; ckcon0 = acc; ( 3 ). required function: s witch mcu running with 32.768khz xtal mode assembly code example: mov ifadrl,#ckcon2 ; index page - p address to ckcon2 call _page_p_sfr_read ; read ck con 2 data anl ifd,#~(xtgs1|xtgs0) ; set xtal to low gain for 32.768khz orl ifd,#(xtale) ; enable xtal oscillating call _page_p_sfr_write ; write data to ck c on2 check_xtor_0: ; check xtal oscillating ready mov a, ckcon 1 jnb acc. 7 ,check_xtor_0 ; waiting for xtor( ckcon 1. 7 ) true anl ifd,#~(oscs1|oscs0) ; switch oscin source to xtal 32.768khz orl ifd,#oscs0 call _page_p_sfr_write ; write data to ck c on2
64 mg82fg5b xx data sheet megawin anl ifd,#~(ihrcoe) ; d isable ihrco call _page_p_sfr_write ; write data to ck c on2 anl ckcon0,#~(scks2|scks1|scks0) ; s ysclk = oscin/1 = 32.768khz c code example: ifadrl = ckcon2; // index page - p address to ckcon2 page_p_sfr_read(); // read ck con 2 data ifd &= ~( xtgs1 | xtgs0 ); // set xtal to low gain for 32.768khz ifd |= xtale; // enable xt al oscillating page_p_sfr_write(); // write data to ckcon2 while( ckcon 1&xtor == 0x00 ); // check xtal oscillating ready // waiting for xtor( ckcon 1. 7 ) true ifd &= ~( oscs1 | oscs0); // switch oscin source to xtal. ifd |= oscs0; page_p_sfr_write (); // write data to ckcon2 ifd &= ~ihrcoe; // disable ihrco if mcu is switched from ihrco page_p_sf r_write(); // write data to ckcon2. ckcon0 & = ~(scks2 | scks1 | scks0); // s ysclk = oscin/1 = 32.768khz ( 4 ). required function: enter watch mode with 2s wake - up duration assembly code example: org 000 5 bh systemflag _isr : or l pcon1,#( wdt f) ; clear wdt flag (write ?1 ?) reti main: or l pcon1,#wdtf ; clear wdtf flag (write ?1 ?) orl wdtcr,#(nsw|enw|ps2|ps1|ps0) ;enabl e wdt and nsw (for watch mode) ; set ps[2:0] = 7 to select wdt period for 1.984s orl sfie,#wdtfie ; enable wdt interrupt orl eie1,#esf ; enable s ystem f lag interrupt setb ea ; enable global interrupt orl pcon0,#pd ; set mcu to power down ; mcu wait for wake -up c code example: void system flag _ isr (void) interrupt 11 { pcon1 | = wdt f; // clear wdt flag (write ?1 ?) } viod main (void) { pcon1 | = wdtf ; // clear wdt flag (write ?1 ?) wdtcr | = (nsw | enw | ps2 | ps1 | ps0); // enable wdt and nsw (for watch mode) // set ps[2:0] = 7 to select wdt period for 1.984s sfie | = wdtfie; // enable wdt interrupt eie1 | = esf; // enable systemflag interrupt ea = 1; // enable g lobal interrupt pcon0 | = pd; // set mcu to power down
megawin mg82fg5b xx data sheet 65 // mcu wait for wake - up } ( 5 ). required function: monitor mode assembly code example: org 000 5 bh systemflag_isr : or l pcon1,#( bo f 0 ) ; clear bod0 flag (write ?1 ?) reti main: mov ifadrl,#pcon2 ; index page - p address to pcon2 call _page_p_sfr_read ; read p con 2 data orl ifd,#awbod0 ; enable bod0 operatin g in power - down mode call _page_p_sfr_write ; write data to p con 2 orl sfie,#bof0ie ; enable bof0 interrupt orl eie1,#esf ; enable systemflag interrupt setb ea ; enable g lobal interrupt orl pcon0,#pd ; set mcu to power down ; mcu wait for wake -up c code example: void systemflag_isr() interrupt 11 { pcon1 | = bof0 ; // clear bod0 flag (write ?1 ?) } void main () { ifadrl = p con2; // index page - p address to pcon2 page_p_sfr_read(); // read p con 2 data ifd | = awbod0; // enable bod0 operatin g in pow er - down mode page_p_sfr_write(); // write data to pcon2 sfie | = bof0i e; // enable bod0 interrupt eie1 | = esf; // enable systemflag interrupt ea = 1; // enable g lobal interrupt pcon0 | = pd; // set mcu to power down // mcu wait for wake -up }
66 mg82fg5b xx data sheet megawin 14. configurable i/o ports the mg82fg5bxx has following i/o ports: p1 .0~p1.7 , p2 .0~p2.7 , p3 .0~p3. 5 , p4. 0, p4. 1 , p4.4, p4.5 , p4.7, p 6 . 0 and p6. 1 . rst pin has a swapped function on p4.7 . if select external crystal oscillator as system clock input, port 6.0 and port 6.1 are configured to xtal2 and xtal1. the exact number of i/o pins available depends upon the package types. see table 14? 1 . table 14 ? 1 . number of i/o pins available package type i/o pins number of i/o ports 32- pin lqfp p1.0~p1.7, p2.0~p2.7, p3.0~p3.5, p4.0, p4.1, p 4.4, p4.5, p4.7(rst), p6.0 (ecki/xtal2), p6.1 (xtal1) 29 or 28 (rst selected) or 27 (rst & ecki selected) or 26 (rst & xtal selected) 14.1. io structure the i/o operating modes are distinguished two groups in mg82fg5bxx . the first group is only for port 3 to support four configurations on i/o operating. these are: quasi - bidirectional (standard 8051 i/o port), push - pull output, input - only (high - impedance input) and open - drain output . t he port 3 default setting is quasi - bidirectional mode with weakly pull - up re sistance. a ll other general port pins belong to the second group. they can be programmed to two output modes, push - pull output and open - drain output with pull - up resistor control . the default setting of this group i/o is open - drain mode with output high, which means input mode with high impedance state . following sections describe the configuration of the all types i/o mode. 14.1.1. port 3 quasi - bidirectional i o structure port 3 pins in quasi - bidirectional mode are similar to the standard 8051 port pins. a quas i - bidirectional port can be used as an input and output without the need to reconfigure the port. this is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. when the pin outputs low, i t is driven strongly and able to sink a large current. there are three pull - up transistors in the quasi - bidirectional output that serve different purposes. one of these pull - ups, called the ?very weak? pull - up, is turned on whenever the port register for the pin contains a logic ?1?. this very weak pull - up sources a very small current that will pull the pin high if it is left floating. a second pull - up, called the ?weak? pull - up, is turned on when the port register for the pin contains a logic ?1? and the pin itself is also at a logic ?1? level. this pull - up provides the primary source current for a quasi - bidirectional pin that is outputting a 1. if this pin is pulled low by the external device, this weak pull - up turns off, and only the very weak pull - up re mains on. in order to pull the pin low under these conditions, the external device has to sink enough current to over - power the weak pull - up and pull the port pin below its input threshold voltage. the third pull - up is referred to as the ?strong? pull - up. this pull - up is used to speed up low - to - high transitions on a quasi - bidirectional port pin when the port register changes from a logic ?0? to a logic ?1?. when this occurs, the strong pull - up turns on for one cpu clocks, quickly pulling the port pin high. the quasi - bidirectional port configu ration is shown in figure 14 ? 1 .
megawin mg82fg5b xx data sheet 67 figure 14? 1 . port 3 quasi - bidirectional i/o vdd port pin 1 clock delay strong very weak weak input data port latch data vdd vdd 14.1.2. port 3 push - pull output structure the pu sh - pull output configuration on port 3 has the same pull - down structure as both the open - drain and the quasi - bidirectional output modes, but provides a continuous strong pull - up when the port register contains a logic ?1?. the push - pull mode may be used wh en more source current is needed from a port output. in addition, the input path of the port pin in this configuration is also the same as quasi - bidirectional mode. the push - pull port configuration is shown in fig ure 14 ? 2 . figure 14? 2 . port 3 push - pull output port pin strong input data port latch data vdd 14.1.3. port 3 input - only (high impedance input) structure the input - only configuration on port 3 is a n input without any pull - up resistors on the pin, as show n in figure 14? 3 . figure 14? 3 . port 3 input - only port pin input data 14.1.4. port 3 open - drain output structure the open - drain output configuration on port 3 turns off all pull - ups and only drives the pull - down transistor of the port pin when the port register contains a logic ?0?. to use this configuration in application, a port pin must have an external pull - up, typically a resistor tied to vdd. the pull - down for this mode is the same as for the quasi -
68 mg82fg5b xx data sheet megawin bidirectional mode. in addition, the input path of the port pin in this configuration is also the same as quasi - bidirectional mode. the open - drain port configuration is shown in figure 14 ? 4 . figu re 14? 4 . port 3 open - drain output port pin input data port latch data 14.1.5. general open - drain output structure the open - drain output configuration on general port pins only drives the pull - down transistor of the port pin when the p ort data r egister contains a logic ?0?. to use this configuration in application, a port pin can select an external pull - up, or an on - chip pull - up by software enabled in pucon0 and pucon1. the general open - drain port configuration is shown in figure 14? 5 . figure 14? 5 . general open - drain output vdd port pin very weak weak input data port latch data vdd puxx 14.1.6. general push - pull output structure the push - pull output configuration on general port pins has the same pull - down structure as the open - drain output modes, but provides a continuous strong pull - up when the port register contains a logic ?1?. the push - pull mode may be used when more source current is needed from a port output. in addition, the input path of the port pin in this con figuration is also the same as open- drain mode. the push - pull port configuration is shown in figure 14 ? 6 .
megawin mg82fg5b xx data sheet 69 figure 14? 6 . general push - pull output port pin strong input data port latch data vdd 14.1.7. general por t input configured a port pin is configured as a digital input by setting its output mode to ?open - drain? and writing a logic ?1? to the associated bit in the port data register. for example, p 1 . 1 is configured as a digital input by setting p 1 m 0 . 1 to a lo gic 0 and p 1 . 1 to a logic 1.
70 mg82fg5b xx data sheet megawin 14.2. i/o port register all i/o port pins on the mg82fg5bxx may be individually and independently configured by software to select its operating mode. only port 3 has four operating modes , as shown in table 14? 2 . two mode registers select the output type for each port 3 pin. table 14 ? 2 . port 3 configuration settings p3m0.y p3m1.y port mode 0 0 quasi - bidirectional 0 1 push - pull output 1 0 input only (high impedance input) 1 1 open - drain output where y=0~ 5 (port pin). the registers p 3 m0 and p 3 m1 are listed in each port description. other general port pins support two operating modes, as shown in ta ble 14 ? 3 . one mode register selects the output type for each port pin. table 14 ? 3 . general port configuration settings pxm0.y port mode 0 open - drain output 1 push - pull output where x = 1, 2, 4, 6 (port num ber), and y=0~7 (port pin). the register s pxm0 are listed in each port description. 14.2.1. port 1 register p1: port 1 register sfr page = 0~f sfr address = 0x90 reset = 1111 - 1111 7 6 5 4 3 2 1 0 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 r/w r/w r/w r/w r/w r/w r/w r/w bit 7~0: p1.7~p1.0 could be only set/cleared by cpu. p1m0: port 1 mode register 0 sfr page = 0~f sfr address = 0x91 reset = 0000 - 0000 7 6 5 4 3 2 1 0 p1m0.7 p1m0.6 p1m0.5 p1m0.4 p1m0.3 p1m0.2 p1m0.1 p1m0.0 r/w r/w r/w r/w r/w r/w r/w r/ w 0: port pin output mode is configured to open - drain. 1: port pin output mode is configured to push - pull. p1aio: port 1 analog input only sfr page = 0~f sfr address = 0x92 reset = 0000 - 0000 7 6 5 4 3 2 1 0 p17aio p16aio p15aio p14aio p13aio p12aio p11aio p10aio r/w r/w r/w r/w r/w r/w r/w r/w 0: port pin has digital and analog input capability. 1: port pin only has analog input only for adc input application. the corresponding port pin register bit will always read as ? 0 ? when this bit is set.
megawin mg82fg5b xx data sheet 71 14.2.2. port 2 register p2: port 2 register sfr page = 0~f sfr address = 0xa0 reset = 1111 - 1111 7 6 5 4 3 2 1 0 p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 r/w r/w r/w r/w r/w r/w r/w r/w bit 7~0: p2.7~p2.0 could be only set/cleared by cpu. p2m0: port 2 mod e register 0 sfr page = 0~f sfr address = 0x95 reset = 0000 - 0000 7 6 5 4 3 2 1 0 p2m0.7 p2m0.6 p2m0.5 p2m0.4 p2m0.3 p2m0.2 p2m0.1 p2m0.0 r/w r/w r/w r/w r/w r/w r/w r/w 0: port pin output mode is configured to open - drain. 1: port pin output mode is configured to push - pull. 14.2.3. port 3 register p3: port 3 register sfr page = 0~f sfr address = 0xb0 reset = xx11- 1111 7 6 5 4 3 2 1 0 -- -- p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 w w r/w r/w r/w r/w r/w r/w bit 7~6: reserved. software must write ? 1 ? on these b its when p 3 is written. bit 5 ~0: p3. 5 ~p3.0 could be only set/cleared by cpu. p3m0: port 3 mode register 0 sfr page = 0~f sfr address = 0xb1 reset = xx00- 0000 7 6 5 4 3 2 1 0 -- -- p3m0.5 p3m0.4 p3m0.3 p3m0.2 p3m0.1 p3m0.0 w w r/w r/w r/w r/w r/w r/w p3m1: port 3 mode register 1 sfr page = 0~f sfr address = 0xb2 reset = xx00- 0000 7 6 5 4 3 2 1 0 -- -- p3m1.5 p3m1.4 p3m1.3 p3m1.2 p3m1.1 p3m1.0 w w r/w r/w r/w r/w r/w r/w 14.2.4. port 4 register p4: port 4 register sfr page = 0~f sfr address = 0xe8 reset = 1x1 1 - xx11 7 6 5 4 3 2 1 0 p4.7 -- p4.5 p4.4 -- -- p4.1 p4.0 r/w w r/w r/w w w r/w r/w bit 7, 5, 4, 1, 0: p4.7, p4.5, p4.4, p4.1 and p4.1 could be set/cleared by cpu.
72 mg82fg5b xx data sheet megawin bit 6, 3, 2: reserved. software must write ? 1 ? on these bits when p4 is wri tten. p4m0: port 4 mode register 0 sfr page = 0~f sfr address = 0xb3 reset = 0x 00- xx00 7 6 5 4 3 2 1 0 p4m0.7 -- p4m0.5 p4m0.4 -- -- p4m0.1 p4m0.0 r/w w r/w r/w w w r/w r/w bit 7, 5, 4, 1, 0: 0: port pin output mode is configured to open - drain. 1: port pin output mode is configured to push - pull. bit 6, 3, 2: reserved. software must write ? 0 ? on these bits when p4m0 is written. 14.2.5. port 6 register p6: port 6 register sfr page = 0~f sfr address = 0xf8 reset = xxxx- xx 11 7 6 5 4 3 2 1 0 -- -- -- -- -- -- p6.1 p6.0 w w w w w w r/w r/w bit 7~ 2: reserved. software must write ? 1 ? on these bits when p 6 is written. bit 1~0: p6.1~p6.0 could be only set/cleared by cpu. p6.1 and p6.0 have the alternated function for crystal oscillating circuit, xtal1 and xtal2. p6m0: port 6 mode register 0 sfr page = 1 only sfr address = 0xb5 reset = xxxx - xx 00 7 6 5 4 3 2 1 0 -- -- -- -- -- -- p6m0.1 p6m0.0 w w w w w w r/w r/w bit 7~2 : reserved. software must write ? 0 ? on these bits when p6m0 is written. bit 1~0: 0: port pin output mode is configured to open - drain. 1: port pin output mode is configured to push - pull. 14.2.6. pull - up control register pucon0: port pull - up control register 0 sfr page = 0 only sfr address = 0xb4 reset = 0000 - 00xx 7 6 5 4 3 2 1 0 p4pu1 p4 pu0 p2pu1 p2pu0 p1pu1 p1pu0 -- -- r/w r/w r/w r/w r/w r/w w w bit 7: port 4 pull - up enable control on high nibble. 0: disable the p4. 7, p4.5, p4.4 pull - up resistor in open - drain output mode. 1: enable the p4. 7, p4.5, p4.4 pull - up resistor in open - drain output mode. bit 6: port 4 pull - up enable control on low nibble. 0: disable the p4. 1, p4.0 pull - up resistor in open - drain output mode. 1: enable the p4.1, p4.0 pull - up resistor in open - drain output mode. bit 5: port 2 pull - up enable control on high nibbl e.
megawin mg82fg5b xx data sheet 73 0: disable the p2.7 ~ p2.4 pull - up resistor in open - drain output mode. 1: enable the p2.7 ~ p2.4 pull - up resistor in open - drain output mode. bit 4: port 2 pull - up enable control on low nibble. 0: disable the p2.3 ~ p2.0 pull - up resistor in open - drain o utput mode. 1: enable the p2.3 ~ p2.0 pull - up resistor in open - drain output mode. bit 3: port 1 pull - up enable control on high nibble. 0: disable the p1.7 ~ p1.4 pull - up resistor in open - drain output mode. 1: enable the p1.7 ~ p1.4 pull - up resistor in ope n - drain output mode. bit 2: port 1 pull - up enable control on low nibble. 0: disable the p1.3 ~ p1.0 pull - up resistor in open - drain output mode. 1: enable the p1.3 ~ p1.0 pull - up resistor in open - drain output mode. bit 1~0 : reserved. software must write ? 0 ? on these bits when p ucon 0 is written. pucon1: port pull - up control register 1 sfr page = 1 only sfr address = 0xb4 reset = xxxx - 00xx 7 6 5 4 3 2 1 0 -- -- -- -- -- p6pu0 -- -- w w w w w r/w w w bit 7 ~ 3 : reserved. software must write ? 0 ? on th e s e bit s when pucon1 is written. bit 2: port 6 pull - up enable control on low nibble. 0: disable the p6.3 ~ p6.0 pull - up resistor in open - drain output mode. 1: enable the p6.3 ~ p6.0 pull - up resistor in open - drain output mode. bit 1 ~ 0: reserved. softwar e must write ? 0 ? on these bits when pucon1 is written.
74 mg82fg5b xx data sheet megawin 14.3. gp io port sample code ( 1 ). required function: set p1.0 to input mode with on - chip pull - up resistor enabled assembly code example: anl p1m0,#~p1m00 ; configure p1.0 to open drain mode setb p1 0 ; set p1.0 data latch to ? 1 ? to enable input mode orl pucon0,#pu10 ; e nable the p1.3~p1.0 on- chip pull - up resistor c code example: p1m0 & = p1m00; // configure p1.0 t o open drain mode p1 0 = 1 ; // set p1.0 data latch to ? 1 ? to enable input mode pucon0 | = pu10; // e nable the p1.3~p1.0 on- chip pull - up resistor
megawin mg82fg5b xx data sheet 75 15. interrupt the mg82 fg5bxx has 1 6 interrupt sources with a four - level interrupt structure. there are several sfrs associated with the four - level interrupt. they are the ie, ip 0l , ip 0 h, e ie 1 , ei p 1l , ei p 1 h , eie2, eip2l, eip2h and xicon. the ip 0 h (interrupt priority 0 high) , e ip 1 h ( extended interrupt priority 1 high) and e ip 2 h ( extended interrupt priority 2 high) registers make the four - level interrupt structure possible. the four priority level interrupt structure allows great flexibility in handling these interrupt sources. 15.1. in terrupt structure table 15? 1 lists all the interrupt sources. the ?request bits? are the interrupt flags that will generate an interrupt if it is enabled by setting the ?enable bit?. of course, the global enable b it ea (in ie 0 register) should have been set previously. the ?request bits? can be set or cleared by software, with the same result as though it had been set or cleared by hardware. that is, interrupts can be generated or pending interrupts can be cancelle d in software. the ?priority bits? determine the priority level for each interrupt. the ?priority within level? is the polling sequence used to resolve simultaneous requests of the same priority level. the ?vector address? is the entry point of an interrup t service routine in the program memory. figure 15 ? 1 show s the interrupt system. each of these interrupts will be briefly described in the following sections. table 15 ? 1 . interrupt sources no source name enable bit request bits priority bits polling priority vector address #1 external interrupt 0, nint0 ex0 ie0 [ px0h, px0l ] (highest) 0003h #2 timer 0 et0 tf0 [ pt0h, pt0l ] ? 000bh #3 external interrupt 1, nint1 e x1 ie1 [ px1h, px1l ] ? 0013h #4 timer 1 et1 tf1 [ pt1h, pt1l ] ? 001bh #5 serial port 0 es0 ri0, ti0 [ ps0h, ps0l ] ? 0023h #6 timer 2 et2 tf2, exf2 [ pt2h, pt2l ] ? 002bh #7 external interrupt 2, nint2 ex2 ie2 [ px2h, px2l ] ? 0033h #8 external inte rrupt 3, nint3 ex3 ie3 [ px3h, px3l ] ? 003bh #9 spi espi spif [ pspih, pspil ] ? 0043h #10 adc eadc adci [ padch, padcl ] ? 004bh #11 pca epca cf, ccfn (n=0~5) [ ppcah, ppcal ] ? 0053h #12 system flag esf (note 1) [ psfh, psfl ] ? 005bh #13 serial po rt 1 es1 ri1, ti1 [ ps1h, ps1l ] ? 0063h #14 keypad interrupt ekb kbif [ pkbh, pkbl ] ? 006bh #15 twi 0 etwi 0 si [ ptwi 0 h, ptwi 0 l ] ? 0073h #16 twi1 etwi1 si1 [ ptwi1h, ptwi1l ] (lowest) 007bh note 1: the system flag interrupt flags include: wdtf, bof0 , bof1, rtcf and mcdf in pcon1, ti0 in s0con, staf and stof in auxr3.
76 mg82fg5b xx data sheet megawin figure 15? 1 . interrupt system nint0 nint1 tcon.5 ( tf0) tcon.tf1 ip0l,ip0 h,eip1l, eip1h,eip2 l,eip2h registers highest priority level interrupt lowest priority level interrupt interrupt polling sequence global enable (ie .ea ) ie.ex0 ie.et0 ie.ex1 ie.et1 ie.es 0 xicon.ex2 xicon.ex3 nint2 ie3 nint3 ie2 ie0 ie1 adcon0.adci xicon.int3h 0 1 0 1 xicon.int2h tcon.it0 tcon.it1 xicon.it 2 xicon.it3 eie1.espi spstat.spif eie1. eadc eie1.esf eie1.es1 eie1.ekb t2con.tf2 t2con.exf2 ie.et2 eie1.epca s1con.ri1 s1con.ti1 kbcon.kbif 0 1 auxr0.int0 h 0 1 auxr0. int1h eie1.etwi0 sicon.si stystem flags pca interrupt flags s0con.ri0 s0con.ti 0 s0cfg.bti eie1.etwi1 si1con.si1
megawin mg82fg5b xx data sheet 77 15.2. i nterrupt source table 15 ? 2 . interrupt source flag n o source name request bits bit location #1 external interrupt 0,nint0 ie0 tcon.1 #2 timer 0 tf0 tcon.5 #3 external interrupt 1,nint1 ie1 tcon.3 #4 timer 1 tf1 tcon.7 #5 serial port 0 ri0, ti0 s0con.0 s0con.1 #6 timer 2 tf2, exf2 t2con.7 t2con.6 #7 e xternal interrupt 2,nint2 ie2 xicon.1 #8 external interrupt 3,nint3 ie3 xicon.5 #9 spi spif spstat.7 #10 adc adci adcon0.4 #11 pca cf, ccfn (n=0~5) ccon.7 ccon.5~0 #12 system flag wdtf , bof1, bof0, rtcf, mcdf, staf, stof, (ti0) pcon1.0 pcon1.1 pcon1.2 pcon1.4 pcon1.5 auxr3.7 auxr3.6 s0con.1 #13 serial port 1 ri1, ti1 s1con.0 s1con.1 #14 keypad interrupt kbif kbcon.0 #15 twi 0 si sicon.3 #16 twi1 si1 si1con.3 the external interrupt n int0, n int1, n int2 and n int3 can each be either level - activated or transition - activated, depending on bits it0 and it1 in register tcon, it2 and it3 in register xicon. the flags that actually generate these interrupts are bits ie0 and ie1 in tcon, ie2 and ie3 in xi con . when an external interrupt is generated, the flag th at generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition ? activated , then the external requesting source is what controls the request flag, rather than the on- chip hardware. the timer0 and tim er1 interrupts are generated by tf0 and tf1, which are set by a rollover in their respective timer/counter registers in most cases. when a timer interrupt is generated, the flag that generated it is cleared by the on - chip hardware when the service routine is vectored to. the serial port 0 interrupt is generated by the logical or of ri 0 and ti 0 . neither of these flags is cleared by hardware when the service routine is vectored to. the service routine should poll ri 0 and ti 0 to determin e which one to request service and it will be cleared by software. the timer2 interrupt is generated by the logical or of tf2 and exf2. just the same as serial port, neither of these flags is cleared by hardware when the service routine is vectored to. spi interrupt is genera ted by spif in spstat, which are set by spi engine finishes a spi transfer . it will not be cleared by hardware when the service routine is vectored to. the adc interrupt is generated by adci in adcon0 . it will not be cleared by hardware when the service r outine is vectored to. the pca interrupt is generated by the logical or of cf, ccf5, ccf4, ccf3, ccf2, ccf1 and ccf0 in ccon. neither of these flags is cleared by hardware when the service routine is vectored to. the service routine should poll these flag s to determine which one to request service and it will be cleared by software.
78 mg82fg5b xx data sheet megawin the system flag interrupt is generated by mcdf, rtcf, bof1, bof0, wdtf, ti0, staf and stof. staf and stof are set by serial interface detection and stored in auxr3. the serial port ti flag is optional to locate the interrupt vector shared with system flag interrupt which is enabled by utie set. the rest flags are stored in pcon1. mcdf is set by mcd activated. rtcf is set by rtc counter overflow. bof1 and bof0 are set by on chip brownout - detector (bod1 and bod0) met the low voltage event. wdtf is set by watch - dog - timer overflow. these flags will not be cleared by hardware when the service routine is vectored to. figure 15 ? 2 s hows the syst em flag interrupt configuration. figure 15? 2 . system flag interrupt configuration pcon1.bof0 eie 1 . esf sfie.bof0ie pcon1.bof1 sfie.bof1ie pcon1.wdtf sfie.wdtfie pcon1.rtcf sfie.rtcfie pcon1.mcdf sfie.mcdfie system flag interrupt s0con.ti0 s0cfg. utie auxr3.staf auxr3.stof sfie.sidfie the serial po rt 1 interrupt is generated by the logical or of ri 1 and ti 1 . neither of these flags is cleared by hardwar e when the service routine is vectored to. the service routine should poll ri 1 and ti 1 to de termine which one to request service and it will be cleared by software. the keypad interrupt is generated by kbcon.kbif, which is set by keypad module meets the i nput pattern. it will not be cleared by hardware when the service routine is vectored to. the twi 0 interrupt is generate by si in sicon, which is set by twi 0 engine detecting a new bus state updated. it will not be cleared by hardware when the service rou tine is vectored to. the twi1 interrupt is generated by si1 in si1con, which is set by twi1 engine detecting a new bus state updated. it will not be cleared by hardware when the service routine is vectored to. all of the bits that generate interrupts can be set or cleared by software, with the same result as though it had been set or cleared by hardware. in other words, interrupts can be generated or pending interrupts can be canceled in software. 15.3. interrupt enable table 15 ? 3 . interrupt enable no source name enable bit bit location #1 external interrupt 0,nint0 ex0 ie.0 #2 timer 0 et0 ie.1 #3 external interrupt 1,nint1 ex1 ie.2 #4 timer 1 et1 ie.3 #5 serial port 0 es0 ie.4 #6 timer 2 et2 ie.5 #7 extern al interrupt 2,nint2 ex2 xicon.2 #8 external interrupt 3,nint3 ex3 xicon.3 #9 spi espi eie1.0 #10 adc eadc eie1.1 #11 pca epca eie1.2
megawin mg82fg5b xx data sheet 79 #12 system flag esf eie1.3 #13 serial port 1 es1 eie1.4 #14 keypad interrupt ekb eie1.5 #15 twi 0 etwi 0 eie1.6 #16 twi1 etwi1 eie1.7 there are 16 interrupt sources available in mg82fg5bxx . each of these interrupt sources can be individually enabled or disabled by setting or clearing an interrupt enable bit in the registers ie , eie1 and xicon . ie also contains a glob al disable bit, ea , which can be cleared to disable all interrupts at once. if ea is set to ?1?, the interrupts are individually enabled or disabled by their corresponding enable bits. if ea is cleared to ?0?, all interrupts are disabled. 15.4. interrupt prior ity the priority scheme for servicing the interrupts is the same as that for the 80c51, except there are four interrupt levels rather than two as on the 80c51. the priority bits (see table 15 ? 1 ) determine the prio rity level of each interrupt. ip 0 l , ip 0 h , eip1l and eip1h are combined to 4 - level priority interrupt . table 15 ? 4 shows the bit values and priority levels associated with each combination. table 15 ? 4 . interrupt priority {ip n h.x , ip n l.x} priority level 11 1 (highest) 10 2 01 3 00 4 each interrupt source has two corresponding bits to represent its priority. one is located in sfr named ip n h and the other in ip n l reg ister. higher - priority interrupt will be not interrupted by lower - priority interrupt request. if two interrupt requests of different priority levels are received simultaneously, the request of higher priority is serviced. if interrupt requests of the same priority level are received simultaneously, an internal polling sequence determine which request is serviced. table 15 ? 2 shows the internal polling sequence in the same priority level and the interrupt vector addre ss. 15.5. interrupt process each interrupt flag is sampled at every system clock cycle. the samples are polled during the next system clock . if one of the flags was in a set condition at first cycle, the second cycle(polling cycle) will find it and the interr upt system will generate an hardware lcall to the appropriate service routine as long as it is not blocked by any of the following conditions. block conditions: ? an interrupt of equal or higher priority level is already in progress. ? the current cycle (pol ling cycle) is not the final cycle in the execution of the instruction in progress. ? the instruction in progress is reti or any write to the ie, ip 0l, ip 0 h , eie1, eip1l and eip1h registers. any of these three conditions will block the generation of the har dware lcall to the interrupt service routine. condition 2 ensures that the instruction in progress will be completed before vectoring into any service routine. condition 3 ensures that if the instruction in progress is reti or any access to ie , ip0l, ip0h, eie1, eip1l or ei p 1h , then at least one or more instruction will be executed before any interrupt is vectored to.
80 mg82fg5b xx data sheet megawin 15.6. nint i input source selection and input filter (i=0~3) the mg82fg5bxx provides flexible nint 0, nint1, nint2 and nint3 source selection on different port pin input which is shared with on - chip serial interface . that will support the additional remote wakeup function for communication peripheral in power - down mode. t he nint i input s can be routed to the interface pin to catch port change and se t them as an interrupt input event to wakeup mcu. int0h (auxr0.0), int1h (auxr0.1), int 2 h (xicon. 3 ) and int 3 h (xicon. 7 ) configure the port change detection level on low/falling or high/rising event. in mcu power - down mode, both of the falling edge or risin g edge configurations of the external interrupt s are force d to level - sensitive op eration. each external interrupt input has a filter option by 3 sysclk recogniz ed to enhance the noise immunity on external interrupt signal. figure 15 ? 3 shows the external interrupts structure and filter behavior. figure 15? 3 . configuration of nint i port pin selection and input filter. nint0 input ie0 0 1 int0h (auxr0.0) it0 = 1 (tcon.0) 0 1 2 3 p3.2 p3.0 p1.6 int0is.1~ 0 (xicfg.5~4) p4.0 (tcon.1) it0 = 0 ie1 it 1 = 1 (tcon.2) (tcon.3) it1 = 0 ie2 it2 = 1 (xicon.0) (xicon.1) it2 = 0 ie3 it3 = 1 (xicon.4) (xicon.5) it3 = 0 0 1 3 clock filter x0flt (xicfg.0) nint1 input 0 1 int1h (auxr0.1) 0 1 2 3 p3.3 p3.1 p1.7 int1is.1~0 (xicfg.7~6) p4.1 0 1 3 clock filter x1flt (xicfg.1) nint2 input 0 1 int2h (xicon.3) 0 1 2 3 p4.4 p2.0 p1.4 int2is.1~0 (auxr2.5~4) p6.1 nint3 input 0 1 int3h (xicon.7) 0 1 2 3 p4.5 p2.1 p1.5 int3is.1~0 (auxr2.7~6) p6.0 0 1 3 clock filter x2flt (xicfg.2) 0 1 3 clock filter x3flt (xicfg.3) ninti input iei set by hardware clear by software sysclk operating example of ninti input filter (xiflt=1, i = 0~3)
megawin mg82fg5b xx data sheet 81 15.7. interrupt register tcon: timer/counter cont rol register sfr page = 0~f sfr address = 0x88 reset = 0000 - 0000 7 6 5 4 3 2 1 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 r/w r/w r/w r/w r/w r/w r/w r/w bit 3: ie1, interrupt 1 edge flag. 0: cleared when interrupt processed on if transition - activated. 1: se t by hardware when external interrupt 1 edge is detected (transmitted or level - activated). bit 2: it1: interrupt 1 type control bit. 0: cleared by software to specif y low level triggered external interr upt 1 . if int1h (auxr0.1) is set, this bit specifies high level triggered on nint1. 1: set by software to specif y falling edge triggered external interrupt 1 . if int1h (auxr0.1) is set, this bit specifies rising edge triggered on nint1. bit 1: ie0, interrupt 0 edge flag. 0: cleared when interrupt processed on if transition - activated. 1: set by hardware when external interrupt 0 edge is detected (transmitted or level - activated). bit 0: it0: interrupt 0 type control bit. 0: cleared by software to specif y low level triggered external interrupt 0 . if int0h (aux r0.0) is set, this bit specifies high level triggered on nint0. 1: set by software to specif y falling edge triggered external interrupt 0 . if int0h (auxr0.0) is set, this bit specifies rising edge triggered on nint 0 . ie: interrupt enable register sfr pag e = 0~f sfr address = 0x a 8 reset = 0x00 - 0000 7 6 5 4 3 2 1 0 ea -- et2 es0 et1 ex1 et0 ex0 r/w w r/w r/w r/w r/w r/w r/w bit 7: ea , all interrupts enable register. 0: global disables all interrupts. 1: global en ables all interrupt s . bit 6: reserved . software must write ? 0 ? on this bit when ie is written. bit 5 : et2, timer 2 interrupt enable register. 0: disable timer 2 interrupt. 1: enable timer 2 interrupt. bit 4: es, serial port 0 interrupt enable register. 0: disable serial port 0 interrupt. 1: enable serial port 0 interrupt. bit 3: et1, timer 1 interrupt enable register. 0: disable timer 1 interrupt. 1: enable timer 1 interrupt. bit 2: ex1, external interrupt 1 enable register. 0: disable external interrupt 1. 1: enable external interrupt 1. bit 1: et0, timer 0 interrupt enable register. 0: disable timer 0 interrupt.
82 mg82fg5b xx data sheet megawin 1: enable timer 1 interrupt. bit 0: ex0, external interrupt 0 enable register. 0: disable external interrupt 0. 1: enable external interrupt 1. xicon: external interrupt contr ol register sfr page = 0~f sfr address = 0xc0 reset = 0000 - 0000 7 6 5 4 3 2 1 0 int3h ex3 ie3 it3 int2h ex2 ie2 it2 r /w r /w r /w r /w r/w r/w r/w r/w bit 7: int3h, nint3 high/rising trigger enable. 0: maintain nint3 triggered on low level or falling e dge on selected p ort pin input . 1: set nint3 triggered on high level or rising edge on selected port pin input . bit 6: ex3, external interrupt 3 enable register. 0: disable external interrupt 3. 1: enable external interrupt 3. when cpu in idle and pd mode , nint3 event will trigger ie3 and have wake - up cpu capability if ex3 is enabled. if ex3 is disabled, ie3 on nint3 will not wake - up cpu from idle or pd mode. bit 5: ie3, external i nterrupt 3 edge flag. 0: c leared by hardware when the interrupt is starting to be serviced. it also could be cleared by cpu. 1: set by hardware when external interrupt edge detected. it also could be set by cpu. bit 4: it3, interrupt 3 type control bit. 0: cleared by cpu to specify low level triggered on nint3. if int3h is set, this bit specifies high level triggered on nint3. 1: set by cpu to specify falling edge triggered on nint3. if int3h is set, this bit specifies rising edge triggered on nint3. bit 3: int2h, nint2 high/rising trigger enable. 0: maintain nint2 triggered on low level or falling edge on selected port pin input . 1: set nint2 triggered on high level or rising edge on selected port pin input . bit 2: ex2, external interrupt 2 enable register. 0: disable external interrupt 2. 1: enable external interrupt 2. when c pu in idle and pd mode, nint2 event will trigger ie2 and have wake - up cpu capability if ex2 is enabled. if ex2 is disabled, ie2 on nint2 will not wake - up cpu from idle or pd mode. bit 1: ie2, external i nterrupt 2 edge flag. 0: c leared by hardware when the interrupt is starting to be serviced. it also could be cleared by cpu. 1: set by hardware when external interrupt edge detected. it also could be set by cpu. bit 0: it2, interrupt 2 type control bit. 0: cleared by cpu to specify low level triggered on ni nt2. if int2h is set, this bit specifies high level triggered on nint2. 1: set by cpu to specify falling edge triggered on nint2. if int2h is set, this bit specifies rising edge triggered on nint2. eie1: extended interrupt enable 1 register sfr page = 0~ f sfr address = 0xad reset = 0 0 00- 0000 7 6 5 4 3 2 1 0 etwi1 etwi 0 ekbi es1 e sf epca eadc espi r/ w r /w r /w r /w r /w r /w r/w r/w
megawin mg82fg5b xx data sheet 83 bit 7: etwi1, enable twi1 interrupt. 0: disable twi1 interrupt. 1: enable twi1 interrupt. bit 6: etwi 0 , enable twi 0 inter rupt. 0: disable twi 0 interrupt. 1: enable twi 0 interrupt. bit 5: ekbi, enable keypad interrupt. 0: disable the interrupt when kbcon.kbif is set in keypad control module. 1: enable the interrupt when kbcon.kbif is set in keypad control module. bit 4: es1 , enable serial port 1 (uart1) interrupt. 0: disable serial port 1 interrupt. 1: enable serial port 1 interrupt. bit 3: esf, enable system flag interrupt. 0: disable the interrupt when the group of { mcdf, rtcf, bof1, bof0, wdtf} in pcon1 , {staf, stof} in auxr3, or ti0 with utie is set . 1: enable the interrupt of the flags of { mcdf, rtcf, bof1, bof0, wdtf} in pcon1 , {staf, stof} in auxr3, or ti0 with utie when the associated system flag interrupt is enabled in sfie. bit 2: epca, enable pca interrupt. 0: d isable pca interrupt. 1: enable pca interrupt. bit 1: ea d c, enable adc interrupt. 0: disable the interrupt when adcon0.adci is set in adc module. 1: enable the interrupt when accon0.adci is se t in adc module. bit 0: espi, enable spi interrupt. 0: disable the interrupt when spstat.spif is set in spi module. 1: enable the interrupt when spstat.spif is set in spi module. sfie: system flag interrupt enable register sfr page = 0~f sfr address = 0x8e reset = 0110 - x000 7 6 5 4 3 2 1 0 sidfie mcdre mcdfie r tcfie -- bof1ie bof0ie wdtfie r/ w r/w r/w r/w w r/w r/w r/w bit 7: sidfie, serial interface (stwi) detection flag interrupt enabled. 0: disable sidf(staf or stof) interrupt. 1: enable sidf(staf or stof) interrupt to share the system flag interrupt. bit 6: mcdre (under verify) bit 5: mcdfie (under verify) bit 4: rtcfie, enable rtcf (pcon1.4) interrupt. 0: disable rtcf interrupt. 1: enable rtcf interrupt. bit 3: reserved. software must write ? 0 ? on this bit when sfie is written. bit 2: bof1ie, enable bof1 (pcon1.2) interrupt. 0: disable bof1 interrupt. 1: enable bof1 interrupt. bit 1: bof0ie, enable bof0 (pcon1.1) interrupt. 0: disable bof 0 interrupt.
84 mg82fg5b xx data sheet megawin 1: enable bof 0 interrupt. bit 0: wdtfie, enable wdtf (pcon1.0) interrupt. 0: disable wdtf interrupt. 1: enable wdtf interrupt. ip0l: interrupt priority 0 low register sfr page = 0~f sfr address = 0xb8 reset = 0 000 - 0000 7 6 5 4 3 2 1 0 px3l px2l pt2l psl pt1l px1l pt0l px0l r/w r/w r/w r/w r/w r/w r/w r/w bit 7: px3l, external interrupt 3 priorit y - l register. bit 6: px2l, external interrupt 2 priority - l register. bit 5: pt2l, timer 2 interrupt priority - l register. bit 4: psl, serial port interrupt priority - l register. bit 3: pt1l, timer 1 interrupt priority - l register. bit 2: px1l, external interr upt 1 priority - l register. bit 1: pt0l, timer 0 interrupt priority - l register. bit 0: px0l, external interrupt 0 priority - l register. ip0h: interrupt priority 0 high register sfr page = 0~f sfr address = 0xb7 reset = 00 0 0 - 0000 7 6 5 4 3 2 1 0 px3h px 2h pt2h psh pt1h px1h pt0h px0h r/w r/w r/w r/w r/w r/w r/w r/w bit 7: px3h, external interrupt 3 priority - h register. bit 6: px2h, external interrupt 2 priority - h register. bit 5: pt2h, timer 2 interrupt priority - h register. bit 4: psh, serial port int errupt priority - h register. bit 3: pt1h, timer 1 interrupt priority - h register. bit 2: px1h, external interrupt 1 priority - h register. bit 1: pt0h, timer 0 interrupt priority - h register. bit 0: px0h, external interrupt 0 priority - h register. eip1l: exten ded interrupt priority 1 low register sfr page = 0~f sfr address = 0xae reset = x00 0 - 0000 7 6 5 4 3 2 1 0 ptwi1l ptwi 0 l pkbl ps1l psfl ppcal padcl pspil r/w r /w r /w r/w r/w r/w r/w r/w bit 7: ptwi1l, twi1 interrupt priority - l register. bit 6: ptwi 0 l , twi 0 interrupt priority - l register. bit 5: pkbl, keypad interrupt priority - l register. bit 4: ps1l, uart1 interrupt priority - l register. bit 3: p sf l, system flag interrupt priority - l register. bit 2: ppcal, pca interrupt priority - l register. bit 1: padcl , adc interrupt priority - l register. bit 0: pspil, spi interrupt priority - l register.
megawin mg82fg5b xx data sheet 85 eip1h: extended interrupt priority 1 high register sfr page = 0~f sfr address = 0xaf reset = x00 0 - 0000 7 6 5 4 3 2 1 0 ptwi1h ptwi 0 h pkbh ps1h psfh ppcah padch psp ih r/w r/w r/w r/w r/w r/w r/w r/w bit 7: ptwi1h, twi1 interrupt priority - h register. bit 6: ptwi 0 h, twi 0 interrupt priority - h register. bit 5: pkbh, keypad interrupt priority - h register. bit 4: ps1 h , uart1 interrupt priority - h register. bit 3: p sfh , sy stem flag interrupt priority - h register. bit 2: ppca h , pca interrupt priority - h register. bit 1: padc h , adc interrupt priority - h register. bit 0: pspi h , spi interrupt priority - h register. auxr0: auxiliary register 0 sfr page = 0~f sfr address = 0xa1 r eset = 000 x - 0000 7 6 5 4 3 2 1 0 p60oc1 p60oc0 p60fd t0xl p4fs1 p4fs0 int1h int0h r/w r/w r/w r/w r/w r/w r/w r/w bit 1: int1h, int1 high/rising trigger enable. 0: remain int1 triggered on low level or falling edge on selected port pin input . 1: set in t1 triggered on high level or rising edge on selected port pin input . bit 0: int0h, int0 high/rising trigger enable. 0: remain int0 triggered on low level or falling edge on selected port pin input . 1: set int0 triggered on high level or rising edge on se lected port pin input . auxr2: auxiliary register 2 sfr page = 0~f sfr address = 0xa3 reset = 0000 - 0000 7 6 5 4 3 2 1 0 int3is1 int3is0 int2is1 int2is0 t1x12 t0x12 t1ckoe t0ckoe r/w r/w r/w r/w r/w r/w r/w r/w bit 7~6: int3is1~0, nint3 input select ion bits which function is defined as following table. int3is1~0 selected port pin of nint3 00 p4.5 01 p2.1 10 p1.5 11 p6.0 bit 5~4: int2is1~0, nint2 input selection bits which function is defined as following table. int2is1~0 selected port pin of ni nt2 00 p4.4 01 p2.0 10 p1.4 11 p6.1
86 mg82fg5b xx data sheet megawin xicfg: external interrupt configured register sfr page = 0~f sfr address = 0xc1 reset = 0000 - 0000 7 6 5 4 3 2 1 0 int1is.1 int1is.0 int0is.1 int0is.0 x3flt x2flt x1flt x0flt r/w r/w r/w r/w r/w r/w r/w r/w bit 7~6: int1is.1~0, nint3 input selection bits which function is defined as following table. int1is.1~0 selected port pin of nint1 00 p3.3 01 p3.1 10 p1.7 11 p4.1 bit 5~4: int0is.1~0, nint0 input selection bits which function is defined as followin g table. int0is.1~0 selected port pin of nint0 00 p3.2 01 p3.0 10 p1.6 11 p4.0 bit 3 : x3flt , int 3 filter enable. 0: disable a 3 - clock filter for int3 input. it remains the default int3 function in mcu. 1: enable a 3 - clock filter for int3 input. bit 2 : x2flt , int 2 filter enable. 0: disable a 3 - clock filter for int2 input. it remains the default int2 function in mcu. 1: enable a 3 - clock filter for int2 input. bit 1 : x1flt , int 1 filter enable. 0: disable a 3 - clock filter for int1 input. it remains the default int1 function in mcu. 1: enable a 3 - clock filter for int1 input. bit 0: x0flt , int 0 filter enable. 0: disable a 3 - clock filter for int0 input. it remains the default int0 function in mcu. 1: enable a 3 - clock filter for int0 input. pcon1: power c ontrol register 1 sfr page = 0~f & p sfr address = 0x97 por = 0 0 10- x000 7 6 5 4 3 2 1 0 swrf exr f mcdf rtcf -- bof1 bof0 wdtf r/w r/w r/ w r/ w w r /w r /w r/w bit 7: swrf, software reset flag. 0: this bit must be cleared by software writing ? 1 ? to it. 1: this bit is set by hardware if a software reset occurs. bit 6: exrf , external reset flag . 0: this bit must be cleared by software writing ? 1 ? to it . 1: this bit is set by hardware if an external reset occurs. bit 5: mcdf. (under verify) bit 4: rtcf, rtc overflow flag. 0: this bit must be cleared by software writing ? 1 ? on it. software writing ? :0 ? is no operation. 1: this bit is only set by hardware when rtcct overflows. writing ? 1 ? on this bit will clear rtcf. bit 3: reserved. software must write ? 0 ? on this bit when pcon1 is written.
megawin mg82fg5b xx data sheet 87 bit 2: bof1, brown - out detection flag 1. 0: this bit must be cleared by software writing ? 1 ? to it . 1: this bit is set by hardware if the operating voltage matches the detection level of brown - out detector 1 (4.2v/3.7/ 2.4/2.0). bit 1: bof0, brown - out detection flag 0. 0: this bit must be cleared by software writing ? 1 ? to it . 1: this bit is set by hardware if the operating voltage matches the detection level of brown - out detector 0 (2.2v). bit 0: wdtf, wdt overflow fl ag. 0: this bit must be cleared by software writing ? 1 ? to it . 1: this bit is set by hardware if a wdt overflow occurs. auxr3: auxiliary register 3 sfr page = 0~f sfr address = 0xa4 reset = 0000 - 0000 7 6 5 4 3 2 1 0 staf stof bpoc1 bpoc0 gf p1s0mi p3 eci p3twi1 r/w r/w r/w r/w r/w r/w r/w r/w bit 7: staf, start flag detection of s twi. 0: clear by firmware by writing ? 0 ? on it. 1: set by hardware to indicate the start condition occurred on s twi bus. bit 6: stof, stop flag detection of s twi. 0: clear by firmware by writing ? 0 ? on it. 1: set by hardware to indicate the st op condition occurred on s twi bus.
88 mg82fg5b xx data sheet megawin 15.8. interrupt sample code ( 1 ). required function: set int0 high level wake - up mcu in power - down mode assembly code example: org 00003h ext_i nt0_isr: to do..... reti main : setb p32 ; orl ip0l,#px0l ; select int0 interrupt priority orl ip0h,#px0h ; orl auxr0,#int0h ; set int0 high level active jb p32,$ ; confirm p3.2 input low setb ex0 ; enable int0 interrupt clr ie0 ; clear int0 f lag setb ea ; enable global i nterrupt orl pcon0,#pd ; set mcu into power down mode c code example: void ext_int0_isr(void) interrupt 0 { t o do?? } void main (void) { p32 = 1; ip0l |= px0l; // select int0 interrupt priority ip0h |= px0h; auxr0 |= int0h; // set int0 high level active while(p32); // confirm p3.2 input low ex0 = 1; // enable int0 interrupt ie0 = 0; // clear int0 f lag ea = 1; // enable global i nterrupt pcon0 |= pd; // set mcu into power down mode }
megawin mg82fg5b xx data sheet 89 16. timers /counters mg82fg5bxx has four 1 6 - bit tim er s / c ounter s : t imer 0 , t ime r 1 and timer 2 . all of them can be configured as timers or event counters. in the ?timer? function, the timer rate is prescaled by 12 clock cycle to incre ase register value . i n other words, it is to count the standard c51 machine cycle. auxr2.t0x12, auxr2.t1x12 and t2mod.t2x12 are the function for timer 0/1/2 to set the timer rate on every clock cycle. it behaves x12 times speed than standard c51 timer function. a dditional pres caler value, sysclk/48 and sysclk/192, can be selected by combining auxr0.t0xl and t0x12 for timer 0 clock input. in the ?counter? function, the register is incre as ed in response to a 1 - to - 0 transition at its corre sponding external input pin, t0 , t1 , t2 o r t3 . in this function, the e xternal input is sampled by every timer rate cycle. when the samples show a high in one cycle and a low in the next cycle, the count is incremented. the new count value appears in the reg ister at the end of t he cycle following the one in which the transition was detected.
90 mg82fg5b xx data sheet megawin 16.1. timer 0 and timer 1 16.1.1. timer 0/1 mode 0 the timer register is configured as a pwm generator. as the count rolls over from all 1s to all 0s, it sets the timer interrupt flag tfx. the counted input is enabled t o the timer when trx = 1 and either gate=0 or intx = 1. mode 0 operation is the same for timer0 and timer1. the pwm function of timer 0/1 is shown in figure 16 ? 1 and figure 16? 2 . figure 16? 1 . timer 0 mode 0 structure auxr 0 . int 0 h 0 1 gate nint0 pin tr0 c/t sysclk /12 t0 pin tf0 t0 interrupt th0[7:0] tl0[7:0] overflow sysclk [t0xl:t0x12] 0 1 8-bit comparator s r q q 0 1 q port i/o t0ckoe t0cko sysclk /48 sysclk /192 0 1 2 3 00: sysclk/12 (default) 01: sysclk 10: sysclk/48 11: sysclk/192 {tl0} >= {th0} {tl0} < {th0} figure 16? 2 . timer 1 mode 0 structure auxr 0 . int 1 h 0 1 gate nint 1 pin tr1 c/t sysclk /12 t1 pin tf1 t1 interrupt th1[7:0] tl1[7:0] overflow sysclk auxr2.t1x12 0 1 0 1 8-bit comparator s r q q 0 1 q port i/o t1ckoe t1cko {tl1} >= {th1} {tl1} < {th1}
megawin mg82fg5b xx data sheet 91 16.1.2. timer 0/1 mode 1 timer 0/1 in mode1 is configured as a 16 bit t imer or counter. the function of gate, intx and trx is same as mode 0. figure 16 ? 3 and figure 16 ? 4 show the mode 1 structure of timer 0 and timer 1. figure 16? 3 . timer 0 mode 1 structure tf 0 t 0 interrupt th 0 [ 7 : 0 ] tl 0 [ 7 : 0 ] overflow auxr 0 . int 0 h 0 1 gate nint0 pin tr0 c/t t0 pin 0 1 0 1 2 3 sysclk /12 sysclk [t0xl:t0x12] sysclk /48 sysclk /192 00: sysclk/12 (default) 01: sysclk 10: sysclk/48 11: sysclk/192 figure 16? 4 . timer 1 mode 1 structure gate tr 1 tf 1 t 1 interrupt th 1 [ 7 : 0 ] tl 1 [ 7 : 0 ] overflow auxr 0 . int 1 h 0 1 nint 1 pin c / t sysclk / 12 t 1 pin sysclk auxr 2 . t 1 x 12 0 1 0 1
92 mg82fg5b xx data sheet megawin 16.1.3. timer 0/1 mode 2 mode 2 configures the timer register as an 8 - bit counter(tlx) with automat ic reload. overflow from tlx not only set tfx, but also reload tlx with the content of thx, which is determined by software. the reload leaves thx unchanged. mode 2 operation is the same for timer0 and timer1. figur e 16 ? 5 and figure 16 ? 6 show the mode 2 structure of timer 0 and timer 1. figure 16? 5 . timer 0 mode 2 structure tf0 t0 interrupt tl0[7:0] overflow th0[7:0] reload auxr0.int0h 0 1 gate nint0 pin tr0 c/t t0 pin 0 1 0 1 2 3 sysclk /12 sysclk [t0xl:t0x12] sysclk /48 sysclk /192 00: sysclk/12 (default) 01: sysclk 10: sysclk/48 11: sysclk/192 figure 16? 6 . timer 1 mode 2 structure gate tr1 tf1 t1 interrupt tl1[7:0] overflow th1[7:0] reload c/t sysclk /12 t1 pin sysclk auxr2.t1x12 0 1 0 1 auxr0.int1h 0 1 nint1 pin
megawin mg82fg5b xx data sheet 93 16.1.4. timer 0/1 mode 3 timer1 in mode3 simply holds its count, the effect is the same as setting tr1 = 1. timer0 in mode 3 enables tl0 and th0 as two separate 8 - bit counters. tl0 uses the timer0 control bits such like c/t, gate, tr0, int0 and tf0. th0 is locked into a timer function (can not be external event counter) and take over the use of tr1, tf1 from timer1. th0 now controls the timer1 interrupt. figure 16 ? 7 show s the mode 3 structure of timer 0. figure 16? 7 . timer 0 mode 3 structure tf0 t0 interrupt tl0[7:0] overflow th0[7:0] tr1 overflow tf1 t1 interrupt auxr0.int0h 0 1 gate nint0 pin tr0 c/t t0 pin 0 1 0 1 2 3 0 1 2 3 sysclk /12 sysclk [t0xl:t0x12] sysclk /48 sysclk /192 00: sysclk/12 (default) 01: sysclk 10: sysclk/48 11: sysclk/192 sysclk /12 sysclk [t0xl:t0 x12] sysclk /48 sysclk /192 00: sysclk/12 (default) 01: sysclk 10: sysclk/48 11: sysclk/192
94 mg82fg5b xx data sheet megawin 16.1.5. timer 0/1 programmable clock - out timer 0 and timer 1 have a clock - out mode (while c/ tx =0 & t xck oe=1). in this mode, timer 0 or tim er 1 operates as 8 - bit auto - reload timer for a programmable clock generator with 50% duty - cycle. the generated clocks come out on p 3 . 4 (t0cko) and p3.5 (t1cko) individually . the input clock ( sysclk/ 1 2 , sysclk, sysclk/48 or sysclk/192) incre ases the 8 - bit t imer , tl0, in timer 0 module . the input clock ( sysclk/ 1 2 or sysclk) incre ase s the 8 - bit timer , tl 1, in timer 1 module. t he timer repeatedly counts to overflow from a loaded value. once overflows occur, the contents of ( t h 0 and th1 ) are loaded into (t l0, t l 1 ) for the consecutive counting. figure 16 ? 8 and figure 16 ? 9 formula gives the formula of timer 0 and timer 1 clock - out frequency . figure 16 ? 10 and figure 16 ? 11 show the clock - out structure of timer 0 and timer 1. figure 16? 8 . timer 0 clock out equation sysclk frequency n x ( 256 C thx) t0 clock-out frequency = ; n=24, if {t0xl,t0x12}=00 ; n=2, if {t0xl,t0x12}=01 ; n=96, if {t0xl,t0x12}=10 ; n=384, if {t0xl,t 0x12}=11 ; c/t = 0 figure 16? 9 . timer 0 clock out equation sysclk frequency n x ( 256 C th1) t1 clock-out frequency = ; n=24, if t1x12=0 ; n=2, if t1x12=1 ; c/t = 0 note: (1) timer 0/1 overflow flag, tf 0/1 , will be set when timer 0/1 overflows but not generate interrupt . (2) for sysclk=12mhz & txx12=0 , timer 0/1 has a programmable output frequency range from 1 . 95k hz to 500k hz. ( 3 ) for sysclk=12mhz & txx12= 1 , timer 0/1 ha s a programmable output frequency range from 23. 43k hz to 6 mhz. ( 4 ) for sysclk=12mhz , t0x12=0 & t0xl=1 , timer 0 has a programmable output frequency range from 488 hz to 125k hz. ( 5 ) for sysclk=12mhz , t xx12=1 & t0xl=1 , timer 0 has a programmable output frequency range from 122 hz to 31.25k hz. figure 16? 10 . timer 0 in clock output mode gate = 0 portn for t 0cko tl0[7:0] overflow th0[7:0] reload auxr2.t0ckoe = 1 d q toggle auxr0.int0h 0 1 nint0 pin tr0 c/t t0 pin 0 1 0 1 2 3 sysclk /12 sysclk [t0xl:t0x12] sysclk /48 sysclk /192 00: sysclk/12 (default) 01: sysclk 10: sysclk/48 11: sysclk/192
megawin mg82fg5b xx data sheet 95 figure 16? 11. t imer 1 in clock output mode gate = 0 tr 1 portn for t1cko tl1[7: 0] overflow th1[7: 0] reload auxr2.t1 ckoe = 1 c/t=0 d q toggle sysclk /12 sysclk auxr2.t1 x12 0 1 auxr0.int1h 0 1 nint1 pin how to program timer 0/1 in clock - out mode ? select auxr2.t0x12 and auxr0.t0xl bit s decide the timer 0 clock source. or select t1x12 in auxr2 register to decide the timer 1 clock source. ? set t 0ck oe /t1ckoe bit in auxr2 register. ? clear c/t bit in t mod register. ? determine the 8 - bit reload value from the formula and enter it in the th0/th1 register. ? enter the same reload value as the initial value in the tl 0/tl1 register . ? set tr 0/tr1 bit in tcon register to start th e timer 0/1 . in the clock - out mode, timer 0/1 rollovers will not generate an interrupt. this is similar to when timer 1 is used as a baud - rate generator. it is possible to use timer 1 as a baud rate generator and a clock generator simultaneously. note, ho wever, that the baud - rate and the clock - out frequency depend on the same overflow rate of timer 1 .
96 mg82fg5b xx data sheet megawin 16.1.6. timer 0 /1 register tcon: timer/counter control register sfr page = 0~f sfr address = 0x88 reset = 0000 - 0000 7 6 5 4 3 2 1 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 r/w r/w r/w r/w r/w r/w r/w r/w bit 7: tf1 , timer 1 overflow flag. 0: cleared by hardware when the processor vectors to the interrupt routine, or clear ed by software . 1: set by har dware on timer/counter 1 overflow , or set by software. bit 6: tr 1, timer 1 run control bit. 0: cleared by software to turn timer/counter 1 off. 1: set by software to turn timer/counter 1 on. bit 5: tf 0, timer 0 overflow flag. 0: cleared by hardware when the processor vectors to the interrupt routine, or clear ed by sof tware . 1: set by har dware on timer/counter 0 overflow , or set by software. bit 4: tr0, timer 0 run control bit. 0: cleared by software to turn timer/counter 0 off. 1: set by software to turn timer/counter 0 on. tmod: timer/counter mode control register sfr page = 0~f sfr address = 0x89 reset = 0000 - 0000 7 6 5 4 3 2 1 0 gate c/t m1 m0 gate c/t m1 m0 r/w r/w r/w r/w r/w r/w r/w r/w | ? ----------------------- timer1 ------------------------- ? | ? -------------------------- timer0 ------------------------ ? | bit 7/3: gate, gating control for timer1/0. 0: disable gating control for timer1/0. 1: enable gating control for tim er 1/0 . when set, timer1/ 0 or counter1 /0 is enabled only when / int 1 or /int0 pin is high and tr 1 or tr0 control bit is set. bit 6/2: c/t, timer for counter function selector. 0: clear for timer operation, input from internal system clock. 1: set for counter operation, input form t1 input pin. bit 5~4/1~0: operating mode selection. m1 m0 operati ng mode 0 0 8 - bit pw m generator for timer0 and timer1 0 1 16 - bit timer/counter for timer0 and timer1 1 0 8 - bit timer/counter with automatic reload for timer0 and timer1 1 1 (timer0) tl0 is 8 - bit timer/counter, th0 is locked into 8 - b it timer 1 1 (timer1) timer/counter1 stopped tl0: timer 0 low byte register sfr page = 0~f sfr address = 0x8a reset = 0000 - 0000 7 6 5 4 3 2 1 0 tl0.7 tl0.6 tl0.5 tl0.4 tl0.3 tl0.2 tl0.1 tl0.0 r/w r/w r/w r/w r/w r/w r/w r/w
megawin mg82fg5b xx data sheet 97 th0: timer 0 h igh byte register sfr page = 0~f sfr address = 0x8c reset = 0000 - 0000 7 6 5 4 3 2 1 0 th0.7 th0.6 th0.5 th0.4 th0.3 th0.2 th0.1 th0.0 r/w r/w r/w r/w r/w r/w r/w r/w tl1: timer 1 low byte register sfr page = 0~f sfr address = 0x8b reset = 0000 - 0 000 7 6 5 4 3 2 1 0 tl1.7 tl1.6 tl1.5 tl1.4 tl1.3 tl1.2 tl1.1 tl1.0 r/w r/w r/w r/w r/w r/w r/w r/w th1: timer 1 high byte register sfr page = 0~f sfr address = 0x8d reset = 0000 - 0000 7 6 5 4 3 2 1 0 th1.7 th1.6 th1.5 th1.4 th1.3 th1.2 th1.1 th1.0 r/w r/w r/w r/w r/w r/w r/w r/w auxr2: auxiliary register 2 sfr page = 0~f sfr address = 0xa3 reset = 0000 - 0000 7 6 5 4 3 2 1 0 int3is1 int3is0 int2is1 int2is0 t1x12 t0x12 t1ckoe t0ckoe r/w r/w r/w r/w r/w r/w r/w r/w bit 3: t1x12 , timer 1 cloc k source select or while c/t=0. 0: c lear to select sysclk /12. 1: set to select sysclk as the clock source . bit 2: t 0 x12 , timer 0 clock sour ce select or while c/t=0. 0: c lear to select sysclk /12. 1: set to select sysclk as the clock source . t0xl, t0x12 time r 0 clock selection 0 0 sysclk/12 0 1 sysclk 1 0 sysclk/48 1 1 sysclk/192 bit 1: t1ckoe, timer 1 clock output enable. 0: disable timer 1 clock output. 1: enable timer 1 clock output on p3.5. bit 0: t0ckoe, timer 0 clock output enable. 0: disable timer 0 clock output. 1: enable timer 0 clock output on p3.4.
98 mg82fg5b xx data sheet megawin 16.2. timer 2 timer 2 is a 16 - bit timer/counter which can operate either as a timer or an event counter, as selected by c/t2 in t2con register. timer 2 has four operating modes: capture, auto - rel oad (up or down counting), baud rate generator and programmable clock - out, which are selected by bits in the t2con and t2mod registers. 16.2.1. capture mode (cp) in the capture mode there are two options selected by bit exen2 in t2con. if exen2=0, timer 2 is a 1 6 - bit timer or counter which, upon overflow, sets bit tf2 (timer 2 overflow flag). this bit can then be used to generate an interrupt (by enabling the timer 2 interrupt bit in the ie register). if exen2=1, timer 2 still does the above, but with the added f eature that a 1 - to - 0 transition or a 0 - to - 1 transition at external input t2ex causes the current value in the timer 2 registers, th2 and tl2, to be captured into registers rcap2h and rcap2l, respectively. in addition, the transition at t2ex causes bit exf2 in t2con to be set, and the exf2 bit (like tf2) can generate an interrupt which vectors to the same location as timer 2 overflow interrupt. the capture mode is illustrated in figure 16? 12. figure 16? 12. timer 2 in capture mode tr2 timer 2 interrupt exf 2 rcap 2 h rcap 2 l tl 2 (8 bits) th 2 (8 bits) tf 2 capture overflow c / t2 sysclk /12 t2 pin sysclk t 2x12 (t2mod.4) 0 1 0 1 exen 2 ( t2con.3 ) t2exh ( t2mod.5 ) t 2 ex pin 16 - bit counter
megawin mg82fg5b xx data sheet 99 16.2.2. auto - reload mode (ar) figure 16? 13 shows dcen=0, which enables timer 2 to count up automatically. in this mode there are two options selected by bit exen2 in t2con register. if exen2=0, then timer 2 counts up to 0ffffh and sets the tf2 (overflow flag) bit upon overflow. this causes the timer 2 registers to be reloaded with the 16 - bit value in rcap2l and rcap2h. the values in rcap2l and rcap2h a re preset by firmware. if exen2=1, then a 16 - bit reload can be triggered either by an overflow or by a 1 - to - 0 transition at input t2ex. this transition also sets the exf2 bit. the timer 2 interrupt, if enabled, can be generated when either tf2 or exf2 are 1. t2exh performs the same function as exen2 but it enables the detecting a 0 - to - 1 transition at input t2ex . figure 16? 13. timer 2 in auto - reload mode (dcen=0) tr 2 timer 2 interrupt exf 2 rcap 2 h rcap 2l tl2 (8 bits) th2 (8 bits) tf2 reload overflow c/t2 sysclk /12 t2 pin sysclk t2x12 (t2mod.4) 0 1 0 1 exen2 ( t2con.3 ) t2exh ( t2mod.5 ) t2ex pin
100 mg82fg5b xx data sheet megawin figure 16? 14 shows dcen=1, which enables timer 2 to count up or down. this mode allows pin t2ex to control the counting direction. when a logic 1 is applied at pin t2ex, timer 2 will count up. timer 2 will overflow at 0ffffh and set the tf2 flag, which can then generate an interrupt if the interrupt is enabled. this overflow also causes the 16 - bit value in rcap2l and rcap2h to be reloaded into the timer registers tl2 and th2. a logic 0 applied to pin t2ex causes timer 2 to count down. the timer will unde rflow when tl2 and th2 become equal to the value stored in rcap2l and rcap2h. this underflow sets the tf2 flag and causes 0ffffh to be reloaded into the timer registers tl2 and th2. in this mode, the t2ex controlled polarity is inverted by t2exh. the exte rnal flag exf2 toggles when timer 2 underflows or overflows. this exf2 bit can be used as a 17th bit of resolution if needed. the exf2 flag does not generate an interrupt in this mode. figure 16? 14. timer 2 in auto - reload mode (dcen=1) count direction 1 = up 0 = down tr2 timer2 interrupt exf2 rcap2h rcap2l tl2 (8 bits) th2 (8 bits) tf2 ffh ffh toggle (up counting reload value) (down counting reload value) c/t2 sysclk /12 t2 pin sysclk t2mod.t2x12 0 1 0 1 t2ex pin t2mod.t2exh 0 1
megawin mg82fg5b xx data sheet 101 16.2.3. baud - rate generator mode (brg) bits tclk and/or rclk in t2con register allow the serial port transmit and receive baud rates to be derived from either timer 1 or timer 2. when tclk=0, timer 1 is used as the serial port transmit baud rate generator. when tclk= 1, timer 2 is used as the serial port transmit baud rate generator. rclk has the same effect for the serial port receive baud rate. with these two bits, the serial port can have different receive and transmit baud rates ? one generated by timer 1, the other by timer 2. figure 16? 15 shows the timer 2 in baud rate generation mode to generate rx clock and tx clock into uart engine (see figure 17 ? 6 . ). the baud rate generation mode is like the auto - reload mode, in that a rollover in th2 causes the timer 2 registers to be reloaded with the 16 - bit value in registers rcap2h and rcap2l, which are preset by firmware. the timer 2 as a baud r ate generator mode is valid only if rclk and/or tclk=1 in t2con register. note that a rollover in th2 does not set tf2, and will not generate an interrupt. thus, the timer 2 interrupt does not have to be disabled when timer 2 is in the baud rate generator mode. also if the exen2 (t2 external enable bit) is set, a 1 - to - 0 transition in t2ex (timer/counter 2 trigger input) will set exf2 (t2 external flag) but will not cause a reload from (rcap2h, rcap2l) to (th2,tl2). therefore when timer 2 is in use as a baud rate generator, t2ex can be used as an additional external interrupt, if needed. when timer 2 is in the baud rate generator mode, one should not try to read or write th2 and tl2. as a baud rate generator, timer 2 is incremented at 1/2 the system clock or asynchronously from pin t2; under these conditions, a read or write of th2 or tl2 may not be accurate. the rcap2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors. the timer sh ould be turned off (clear tr2) before accessing the timer 2 or rcap2 registers. note: refer to section ? 17.7.3 baud rate in mode 1 & 3 ? to get baud rate setting value w hen using timer 2 as the baud rate generator. figure 16? 15. timer 2 in baud - rate generator mode tr 2 smod 1 rcap 2 h rcap 2 l tl2 (8 bits) th2 (8 bits) reload tclk rclk tx clock rx clock timer 1 overflow exf2 timer2 interrupt c/t2 sysclk /2 t2 pin sysclk t2x12 (t2mod.4) 0 1 0 1 2 0 1 0 1 0 1 overflow timer 2 overflow (t2of) 1. to t2cko exen2 ( t2con.3 ) t2ex pin t2exh ( t2mod.5 )
102 mg82fg5b xx data sheet megawin 16.2.4. timer 2 programmable clock output timer 2 has a clock - out mode (while cp/rl2=0 & t2oe=1). in this mode , timer 2 operates as a programmable clock generator with 50% duty - cycle. the generated clocks come out on p1.0. the input clock ( sysclk/2 or sysclk) increments the 16 - bit timer (th2, tl2). the timer repeatedly counts to overflow from a loaded value. once overflows occur, the contents of (rcap2h, rcap2l) are loaded into (th2, tl2) for the consecutive counting. figure 16 ? 16 gives the formula of timer 2 clock - out frequency: fig ure 16 ? 17 shows the clock structure of timer 2. figure 16? 16 . timer 2 clock out equation sysclk frequency n x ( 65536 C ( rcap 2 h , rcap 2 l )) t 2 clock - out frequency = ; n = 4 , if t 2 x 12 = 0 ; n = 2 , if t 2 x 12 = 1 note: (1) timer 2 overflow flag, tf2, will be set when timer 2 overflows but not generate interrupt. (2) for sysc lk=12mhz & t2x12=0 , timer 2 has a programmable output frequency range from 45.7hz to 3mhz. ( 3 ) for sysclk=12mhz & t2x12=1 , timer 2 has a programmable output frequency range from 91. 5 hz to 6 mhz. figure 16? 17. timer 2 in clock - out mode tr 2 ( t 2 con . 2 ) rcap 2 h rcap 2 l tl 2 ( 8 bits ) th 2 ( 8 bits ) reload sysclk / 2 sysclk 0 1 overflow t 2 x 12 ( t 2 mod . 4 ) c / t 2 = 0 ( t 2 con . 1 ) t 2 oe ( t 2 mod . 1 ) portn for t 2 cko d q toggle timver 2 overflow ( t 2 of ) how to program timer 2 in clock - out mode ? select t2x12 bit in t 2mod register to decide the timer 2 clock source. ? set t2oe bit in t2mod register. ? clear c/t2 bit in t2con register. ? determine the 16 - bit reload value from the formula and enter it in the rcap2h and rcap2l registers. ? enter the same reload value as the initial value in the th2 and tl2 registers. ? set tr2 bit in t2con register to start the timer 2. in the clock - out mode, timer 2 rollovers will not gene rate an interrupt. this is similar to when timer 2 is used as a baud - rate generator. it is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. note, however, that the baud - rate and the clock - out frequency depend on the sa me overflow rate of timer 2.
megawin mg82fg5b xx data sheet 103 16.2.5. timer 2 register t2con: timer 2 control register sfr page = 0 ~f sfr address = 0xc8 reset = 0000 - 0000 7 6 5 4 3 2 1 0 tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 r/w r/w r/w r/w r/w r/w r/w r/w bit 7: tf2 , timer 2 overf low flag. 0: tf2 m ust be cleared by soft ware . 1: tf2 is set by a timer 2 overflow happens . tf2 will not be set when either rclk=1 or tclk=1. bit 6: exf2 , timer 2 external flag. 0: exf2 must be cleared by soft ware . 1: timer 2 external flag set when either a capture or reload is caused by a negative transition on t2ex pin and exen2=1 or a positive transition on t2ex and t2exh=1 . when timer 2 interrupt is enabled, exf2=1 will cause the cpu to vector to the timer 2 interrupt routine. exf2 does not cause an int errupt in up/down mode (dcen = 1). bit 5: rclk , receive clock flag. 0: c auses timer 1 overflow to be used for the receive clock. 1: c auses the serial port to use timer 2 overflow pulses for its receive clock in modes 1 and 3. bit 4: tclk , transmit clock flag. 0: c auses timer 1 overflows to be used for the transmit clock. 1: c auses the serial port to use timer 2 overflow pulses for its transmit clock in modes 1 and 3. bit 3: exen2 , timer 2 external enable flag on a negative transition of t2ex pin. 0: caus e timer 2 to ignore negative transition events at t2ex pin. 1: a llows a capture or reload to occur as a result of a 1 - to - 0 transition on t2ex pin if timer 2 is not being used to clock the serial port 0 . if timer 2 is configured to clock the serial port 0, the t2ex remains the external transition detection and reports on exf2 flag with timer 2 interrupt. bit 2: tr2 , timer 2 run control bit. 0: stop the timer 2. 1: start the timer 2. bit 1: c/t2 , timer or counter sele ct or . 0: s elect timer 2 as internal time r function. 1: s elect timer 2 as external event counter (falling edge triggered). bit 0: cp/ - rl2 , capture/reload flag. 0: a uto - reloads will occur either with timer 2 overflows or negative transitions at t2ex pin when exen2=1. 1: c aptures will occur on neg ative transitions at t2ex pin if exen2=1. when either rclk=1 or tclk=1, this bit is ignored and the timer is forced to auto - reload on timer 2 overflow. t2mod: timer 2 mode register sfr page = 0~f sfr address = 0xc9 reset= xx00 - xx00 7 6 5 4 3 2 1 0 -- -- t2exh t2x12 -- -- t2oe dcen2 w w r /w r/w w w r/w r/w bit 7~6: reserved. software must write ? 0 ? on these bits when t2mod is written. bit 5: t 2 exh, timer 2 external enable flag on a positive transition of t2ex pin. 0: cause timer 2 to ignore positiv e transition events at t2ex pin.
104 mg82fg5b xx data sheet megawin 1: a llows a capture or reload to occur as a result of a 0 - to1 transition on t2ex pin if timer 2 is not being used to clock the serial port 0 . if timer 2 is configured to clock the serial port 0, the t2ex remains the externa l transition detection and reports on exf2 flag with timer 2 interrupt. bit 4: t2x12, timer 2 clock source selector. 0: select sysclk/12 as timer 2 clock source while t2con.c/t2 = 0 in capture mode and auto - reload mode. if in baud - rate generator mode, it selects the sysclk/2 as timer 2 clock source while t2con.c/t2 = 0. 1: select sysclk as timer 2 clock source while t2con.c/t2 = 0 in capture mode and auto - reload. if in baud - rate generator mode, it selects the sysclk as timer 2 clock source while t2con.c/t2 = 0. bit 3~2: reserved. software must write ? 0 ? on these bits when t2mod is written. bit 1: t2oe, timer 2 clock - out enable bit . 0 : d isable timer 2 clock output. 1 : e nable timer 2 clock output. bit 0: d cen 2, timer 2 down - counting enable bit. 0: timer 2 always keeps up - counting. 1: enable timer 2 down - counting ability. when the dcen 2 is cleared, which m akes the function of timer 2 as the same as the standard 8052 (always counts up). when dcen2 is set , timer 2 can count up or count down according to the l ogic level of the t2ex pin (p1.1). table 16 ? 1 shows the operation modes of timer 2. table 16 ? 1 . t2 mode tr2 t2oe rclk + tclk cp/ - rl2 dcen 2 mode 0 0 x x x (off) 1 1 0 0 0 timer 2 clock output ( c/t2=0 ) 1 0 1 0 0 baud - r ate generator 1 1 1 0 0 clock output & baud - rate generator ( c/t2=0 ) 1 0 0 1 0 16 - bit capture 1 0 0 0 0 16 - bit auto - reload (counting - up only) 1 0 0 0 1 16 - bit auto - reload (counting - up or counting - down) tl2: timer 2 low byte register sfr page = 0 ~f sfr address = 0xcc reset = 0000 - 0000 7 6 5 4 3 2 1 0 tl2.7 tl2.6 tl2.5 tl2.4 tl2.3 tl2.2 tl2.1 tl2.0 r/w r/w r/w r/w r/w r/w r/w r/w th2: timer 2 high byte register sfr page = 0 ~f sfr address = 0xcd reset = 0000 - 0000 7 6 5 4 3 2 1 0 th2.7 th2.6 th2.5 th2.4 th2.3 th2.2 th2.1 th2.0 r/w r/w r/w r/w r/w r/w r/w r/w rcap2l: timer 2 capture low byte register sfr page = 0 ~f sfr address = 0xca reset = 0000 - 0000 7 6 5 4 3 2 1 0 rcap2l.7 rcap2 l.6 rcap2l.5 rcap2l.4 rcap2l.3 rcap2l.2 rcap2l.1 rcap2l.1 r/w r/w r/w r/w r/w r/w r/w r/w
megawin mg82fg5b xx data sheet 105 rcap2h: timer 2 capture high byte register sfr page = 0 ~f sfr address = 0xcb reset = 0000 - 0000 7 6 5 4 3 2 1 0 rcap2h.7 rcap2h.6 rcap2h.5 rcap2h.4 rcap2h.3 r cap2h.2 rcap2h.1 rcap2h.0 r/w r/w r/w r/w r/w r/w r/w r/w
106 mg82fg5b xx data sheet megawin 16.3. timer sample code ( 1 ). required function: idle mode with t0 wake - up frequency 32 0hz, sysclk = ilrco assembly code example: org 0000bh time0_isr: to do? reti main : ; (unsigned short value) //switch sysclk to ilrco mov ifadrl,#(ckcon2) ; index page -p address to ckcon2 call _page_p_sfr_read ; read ck c on2 data anl ifd,#~(oscs1 | osc s0) ; switch oscin source to ilrco orl ifd,#(oscs1) call _page_p_sfr_write ; write data to ck c on2 anl ifd,#~(xtale | ihrcoe) ; disable xtal and i hrco call _page_ p_sfr_write ; write data to ck c on2 or l auxr2,#t0x12 ; select sysclk/1 for timer 0 clock input an l auxr0,# ~ t0xl ; mov th0,# (256 -100) ; set timer 0 overflow rate = sysclk x 100 mov tl0,# (256- 100 ) ; anl tmod,#(0f0h|t0m1) ; set timer 0 to mode 2 orl tmod,#t0m1 ; clr tf0 ; clear timer 0 flag orl ip0l,#pt0l ; select timer 0 interrupt priority orl ip0h,#pt0h ; setb et0 ; enable timer 0 interrupt setb ea ; enable global interrupt setb tr0 ; start timer 0 running orl pcon0,#idl ; set mcu into idle mode c code example: void time0_isr(void) interrupt 1 { t o do? } void main ( void ) { ifadrl = ckcon2; // index page -p address to ckcon2 page_p_sfr_read(); // read ckcon2 data. ifd = ~(oscs1 | oscs0); // switch oscin source to ilrco ifd |= oscs1; page_p_sfr_wr ite(); // write data to ckcon2 ifd &= ~(xtale | ihrcoe); // disable xtal and ihrco page_p_sfr_write(); // write data to ckcon2 auxr2 | = t0x12; // select syscl k/1 for timer 0 clock input auxr0 &= ~ t0xl; th0 = tl0 = (256 -100 ) ; // set timer 0 overflow rate = sysclk x 100 tmod &= 0xf0; // set timer 0 to mode 2 tmod |= t0m1; tf0 = 0; // clear time r 0 flag
megawin mg82fg5b xx data sheet 107 ip0l |= pt0l; // select timer 0 interrupt priority ip0h |= pt0h; et0 = 1; // enable timer 0 interrupt ea = 1; // e nable global interrupt tr0 = 1; // start timer 0 running pcon0=idl; // set mcu into idle mode } (2). required function: set timer 0 clock output by sysclk/48 input assembly code exampl e: clr tr0 ; anl p3m0,#0efh ; set p3 . 4 (t0 cko) to push - pull output orl p3m1,#010h ; orl auxr2,#t0ckoe ; enable t0cko anl auxr2,#~t 0x12 ; select sysclk/48 for timer 0 clock input orl auxr0,#t0xl ; mov th0,#0ffh ; mov tl0,#0ffh ; anl tmod,#0f0h ; set timer 0 to mode 2 orl tmod,#t0m1 ; setb tr0 ; start timer 0 running c code example: tr0 = 0; p3m0 &= 0xef; // set p3 . 4 (t0 cko) to push - pull output p3m1 |= 0x10; auxr2 |= t0ckoe; // enable t0cko auxr2 &= ~t0x12; // select sysclk/48 for timer 0 clock input auxr0 |= t0xl; th0 = tl0 = 0xff; tmod &= 0xf0; // set timer 0 to mode 2 tmod |= t0m1; tr0 = 1; // start timer 0 running (3). required function: set timer 1 clock output by sysclk input assembly code example: orl p3m1,#020h ; set p3 .5( t 1cko) to push - pull output anl p3m0,#0dfh ; orl auxr2,#(t1x12|t1ckoe) ; select sysclk for timer 1 clock input ; enable t1cko mov th1,#0ffh ; mov tl1, #0ffh ; anl tmod,#00fh ; set timer 1 to mode 2 orl tmod,#t1m1 ; setb tr1 ; start timer 1 running
108 mg82fg5b xx data sheet megawin c code example: p3m1 |= 0x20; // set p3 .5( t 1cko) to push - pull output p3m0 &= 0xdf; auxr2 |= (t1x12|t1ckoe); // select sysclk for timer 1 clock input // enable t1cko th1 = tl1 = 0xff; tmod &= 0x0f ; // set timer 1 to mode 2 tmod |= t1m1; tr1 = 1; // start timer 1 running
megawin mg82fg5b xx data sheet 109 17. serial port 0 ( uart 0) the serial port 0 of mg82fg5bxx support full - duplex transmission , meaning it can transmit and receive simultaneously. it is also receive - buffered, meaning it can commence reception of a second byte before a previously received byte ha s been read from the register. however, if the first byte still hasn?t been read by the time reception of the second byte is complete, one of the bytes will be lost. the serial port receive and transmit registers are both accessed at s pecial f unction r egister s 0 buf. writing to s 0 buf loads the transmit register, and reading from s 0 buf accesses a physi cally s eparate receive register. the serial port can operate in 5 modes: mode 0 provides synchronous communication while modes 1, 2, and 3 provide asynchronous communication . the asynchronous communication operates as a full - duplex universal asynchronous receive r and transmitter (uart) , which can transmi t and rece ive simultaneously and at different baud rates . mode 4 in uart0 supports spi master operation which data rate setting is same as mode 0. mode 0: 8 data bits ( lsb first ) are transmitted or received throu gh r x d 0 . t x d 0 always outputs the shift clock. the baud rate can be selected to 1/12 or 1/ 4 the system clock frequency by urm0x 3 setting in s0cfg register. in mg82fg5bxx , the clock polarity of serial port mode 0 can be selected by software. i t is decided by p3.1 state before serial data shift in or shift out. figure 17 ? 4 and figure 17? 5 show the clock polarity waveform in mode 0. mode 1: 10 bits are transmitted through t x d 0 or received through r x d 0. the frame data includes a start bit (0), 8 data bits (lsb first), and a stop bit (1) , as shown in figure 17? 1 . on receive, the stop bit would be loaded into rb8 0 in s 0 con register . the bau d rate is variable. figure 17? 1 . mode 1 data frame d 1 d2 d3 d4 d5 d6 d7 mode 1 start d0 stop 8-bit data mode 2: 11 bits are transmitted through t x d 0 or received through r x d 0. the frame data includes a start bit (0), 8 data bits (lsb first), a programmab le 9th data bit, and a stop bit (1) , as shown in figure 17 ? 2 . on transmit, the 9th data bit comes from tb8 0 in s 0 con register can be as signed the value of 0 or 1. on receive, the 9th data bit would be loaded in to r b8 0 in s 0 con register , while the stop bit is ignored. the baud rate can be configured to 1/32 or 1/64 the system clock frequency . figure 17? 2 . mode 2, 3 data frame d 1 d2 d3 d4 d5 d6 mode 2, 3 start d0 stop d8 d7 9-bit data mode 3: mode 3 is the same as mode 2 except the baud rate is variable . in all four modes, transmission is initiated by any instruction that uses s 0 buf as a destination register. in mode 0, r eception is initiated by the condition ri 0 =0 and ren 0 =1. in the other modes , r eception is initiated b y the incoming start bit with 1 - to - 0 transition if ren 0 =1. in addition to the standard operation , the uart 0 can perform framing error detect ion by looking for missing stop bits, and automatic address recognition.
110 mg82fg5b xx data sheet megawin 17.1. serial port 0 mode 0 serial data enter and exits through r x d 0 . t x d 0 outputs the shift clock. 8 bits are transmitted/received: 8 data bits (lsb first). the shift clock source can be selected to 1/12 or 1/ 4 the system clock frequency by urm0x 3 setting in s0cfg register. figure 17? 3 shows a simplified functional diagram of the serial port 0 in mode 0 . transmission is initiated by any instruction that uses s 0 buf as a destination register. the ? write to s0buf ? signal triggers the uart0 engine to start the t ransmission. the data in the s0buf would be shifted into the rxd0(p3.0) pin by each raising edge shift clock on the txd0(p3.1) pin. after eight raising edge of shift clocks passing, ti would be asserted by hardware to indicate the end of transmission. figure 17 ? 4 shows the transmission waveform in mode 0. reception is initiated by the condition ren 0 =1 and r i 0 =0. at the next instruction cycl e, the serial port 0 controller writes the bits 11111110 to the receive shif t register, and in the next clock phase activates r eceive . r eceive enable s s hift clock which directly comes from rx clock to the alternate output function of txd0 pin . when receive is active, the contents on the rxd0 pin would be sampled and shifted into shift register by falling edge of shift clock. after eight falling edge of shift clock, ri0 would be asserted by hardware to indicate the end of reception. figure 17 ? 5 shows the reception waveform in mode 0. when txd0 is assigned on p3.1, t he clock polarity can be selected by software setting on p3.1 data latch before serial transfer shifted. if p3.1 is set to logic high, the clock polarity is same as standard 8051. if p3.1 data latch is cleared to logic low, the c lock polarity is inverted to standard 8051 uart mode 0. figure 17? 3 . serial port 0 mode 0 uart engine 80 c 51 internal bus txbuf rxbuf 80c51 internal bus ren0 ri0 read s0buf write s0buf urm0x3 tx clock rx clock sysclk 0 1 ti0 ri0 serial port 0 interrupt shift-clock rxd0 alternated for input/output function txd0 alternated for output function rxstart 4 12 bti system flag interrupt utie esf
megawin mg82fg5b xx data sheet 111 figure 17? 4 . mode 0 transmission waveform txd 0 rxd0 ti0 ri0 txd0 d1 d2 d3 d4 d5 d6 d7 write to s0buf d0 software set/clear txd0 assigned port pin to initial clock polarity, such as p3.1 figure 17? 5 . mode 0 reception waveform d 1 d 2 d 3 d 4 d 5 d 6 d 7 write to s 0 con txd 0 rxd 0 ti 0 d 0 ri 0 set ren 0 , clear ri 0 software set / clear txd 0 assigned port pin to initial clock polarity , such as p 3 . 1 txd 0
112 mg82fg5b xx data sheet megawin 17.2. serial port 0 mode 1 10 bits are transmitted through t x d 0 , or received through r x d 0 : a start bit (0), 8 data bits (lsb first), and a stop bit (1). on receive, the stop bi t goes into rb8 0 in s 0 con . the baud rate is determined by the timer 1 or timer 2 overflow rate. figure 17 ? 1 shows the data frame in mode 1 and figure 17? 6 shows a simplifie d functional diagram of the serial port in mode 1 . transmission is initiated by any instruction that uses s 0 buf as a destination register. the ?write to s 0 buf? signal requests the uart0 engine to start the transmission. after receiving a transmission requ est, the uart0 engine would start the transmission at the raising edge of tx clock. the data in the s0buf wo uld be serial output on the txd0 pin with the data frame as shown in figure 17? 1 and data width depend on tx clock. after the end of 8th data transmission, ti0 would be asserted by hardware to indicate the end of data transmission. reception is initiated when serial port 0 controller detected 1 - to - 0 transition at r x d 0 sampled by rck . the data on the rxd0 pin would be sampled by bit detector in serial port 0 controller. after the end of stop - bit reception, ri0 would be asserted by hardware to indicate the end of data reception and load stop - bit into rb80 in s0con register. figure 17? 6 . serial port mode 1, 2, 3 uart engine txbuf rxbuf rxd 0 txd0 smod 1 rclk tclk tx clock timer 1 overflow 1 1 0 0 0 1 timer 2 overflow sysclk / 2 0 1 0 1 0 1 rx clock sm 00 sm 1 sm10 sm10 tb 80 mode 1 , 3 clock source mode 2 clock source rck smod 2 80 c51 internal bus read s0buf 80 c51 internal bus write s0buf 2 2 16 16 stop-bit 9th-bit 0 1 sm 00 rb 80 ti0 ri0 serial port 0 interrupt bti system flag interrupt utie esf
megawin mg82fg5b xx data sheet 113 17.3. serial port 0 mode 2 and mode 3 11 bits are transmitted through t x d 0 , or received through r x d 0 : a start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). on transm it, the 9th data bit (tb8 0 ) can be assigned the value of 0 or 1. on receive, the 9th data bit goes into rb8 0 in s 0 con . the baud rate is programmable to select one of 1/16, 1/32 or 1/64 the system clock frequency in mode 2. mode 3 may have a variable baud r ate generated from timer 1 or timer 2. figure 17? 2 shows the data frame in mode 2 and mode 3. figure 17 ? 6 show s a functional diagram of the serial port in mode 2 and mode 3. the receive portion is exactly the same as in mode 1. the transmit portion differs from mode 1 only in the 9th bit of the transmit shift register. the ? write to s0buf ? signal requests the serial port 0 controller to load tb80 into the 9th bit position of the transmit shi f t register and starts the transmission. after receiving a transmission request, the uart0 engine would start the transmission at the raising edge of tx clock. the data in the s0buf would be serial output on the txd0 pin with the data fr ame as shown in figure 17 ? 2 and data width depend on tx clock. after the end of 9th data transmission, ti0 would be asserted by hardware to indicate the end of data transmission. reception is initiated when the ua rt0 engine detected 1 - to - 0 transition at r x d 0 sampled by rck . the data on the rxd0 pin would be sampled by bit detector in uart0 engine. after the end of 9th data bit reception, ri0 would be asserted by hardware to indicate the end of data reception and lo ad the 9th data bit into rb80 in s0con register. in all four modes, transmission is initiated by any instruction that use s 0 buf as a destination register. reception is initiated in mode 0 by the condition ri 0 = 0 and ren 0 = 1. reception is initiated in t he other modes by the incoming start bit with 1 - to - 0 transition if ren 0 =1. 17.4. frame error detection when used for framing error detect ion, the uart 0 looks for missing stop bits in the communication. a missing stop bit will set the fe bit in t he s 0 con regis ter. the fe bit shares the s 0 con.7 bit with sm0 0 and the function of s 0 con.7 is determined by smod0 bit ( pcon .6) . if smod0 is set then s 0 con.7 functions as fe. s 0 con.7 functions as sm0 0 when smod0 is cleared. when s0con.7 functions as fe , it can only be cl ear ed by firmware. refer to figure 17 ? 7 . figure 17? 7 . uart 0 frame error detection d 1 d2 d3 d4 d5 d6 start d0 stop d8 d7 9-bit data set fe bit if stop=0 sm00 to uart mode control pcon0.smod0 s0con ri0 ti0 rb80 tb80 ren0 sm20 sm10 sm00/ fe
114 mg82fg5b xx data sheet megawin 17.5. multiprocessor communications modes 2 and 3 have a special provision for m ultiprocessor communications as shown in figure 17? 8 . in these two modes, 9 data bits are received. the 9th bit goes into rb8 0 . then comes a stop bit. the port can be programmed such that when the stop bit is recei ved, the serial port interrupt will be activated only if rb8 0 =1. this feature is enabled by setting bit sm2 0 (in s 0 con register). a way to use this feature in multiprocessor systems is as follows: when the master processor wants to transmit a block of dat a to one of several slaves, it first sends out an address byte which identifies the target slave. an address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. with sm2 0 =1, no slave will be interrupted by a data byte. an address byte, however, will interrupt all slaves, so that each slave can examine the received byte and check if it is being addressed. the addressed slave will clear its sm2 0 bit and prepare to receive the data bytes that will be coming. the slav es that weren?t being addressed leave their sm2 0 set and go on about their business, ignoring the coming data bytes. sm2 0 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop bit. in a mode 1 reception, if sm2 0 =1, the recei ve interrupt will not be activated unless a valid stop bit is received. figure 17? 8 . uart 0 multiprocessor communications slave 3 slave 2 slave 1 master r vcc pull-up tx rx rx rx rx tx tx tx 17.6. automatic address recognition automatic address recognition is a feature which allows the uart 0 to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. this feature saves a great deal of firmware overhead by eliminating the need for the firmware to examine every serial address which passes by the serial port. this feature is enabled by setting the sm2 0 bit in s 0 con . in the 9 bit uart modes, mode 2 and mode 3, the receive interrupt flag (ri 0 ) will be automatically set when the received byte contains either the ?given? address or the ?broadca st? address. the 9 - bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. automatic address recognition is shown in figure 17 ? 9 . the 8 bit mode i s called mode 1. in this mode the ri flag will be set if sm2 0 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a given or broadcast address. mode 0 is the shift register mode and sm2 0 i s ignored. using the automatic address recognition feature allows a master to selectively communicate with one or more slaves by invoking the given slave address or addresses. all of the slaves may be contacted by using the broadcast address. two special function registers are used to define the slave?s address, saddr, and the address mask, saden. saden is used to define which bits in the saddr are to be used and which bits are ?don?t care?. the saden mask can be logically anded with the saddr to create t he ?given? address which the master will use for addressing each of the slaves. use of the given address allows multiple slaves to be recognized while excluding others. the following examples will help to show the versatility of this scheme:
megawin mg82fg5b xx data sheet 115 slave 0 s add r = 1100 0000 saden = 1111 1101 given = 1100 00x0 slave 1 saddr = 1100 0000 saden = 1111 1110 given = 1100 000x in the above example saddr is the same and the saden data is used to differentiate between the two slaves. slave 0 requires a 0 in bit 0 and i t ignores bit 1. slave 1 requires a 0 in bit 1 and bit 0 is ignored. a unique address for slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. a unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. both slaves c an be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). thus, both could be addressed with 1100 0000. in a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: slave 0 saddr = 1100 0000 saden = 1111 1001 given = 1100 0xx0 slave 1 saddr = 1110 0000 saden = 1111 1010 given = 1110 0x0x slave 2 saddr = 1110 0000 saden = 1111 1100 given = 1110 00xx in the above example the differentiation among the 3 slaves is i n the lower 3 address bits. slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 0101. slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. t o select slaves 0 and 1 and exclude slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. the broadcast address for each slave is created by taking the logical or of saddr and saden. zeros in this result are tre at ed as don?t - cares. in most cases, interpreting the don?t - cares as ones, the broadcast address will be ff hexadecimal. upon reset saddr (sfr address 0 x a9) and saden (sfr address 0 x b9) are l oa ded with 0s. this produces a given address of all ?don?t cares? as wel l as a broadcast address of all ?don?t cares?. this effectively disables the automatic addressing mode and allows the micro - controller to use standard 80c51 type uart drivers which do not make use of this feature. figure 17? 9 . auto - address recognition d 1 d2 d3 d4 d5 d6 start d0 stop d8 d7 9-bit data comparator receive address d0~d7 programmed address addr_match s0con ri0 ti0 rb80 tb80 ren0 sm20 sm10 sm00/ fe note: (1) after address matching(addr_match=1), clear sm2 0 to receive data bytes (2) after all data bytes have been received, set sm2 0 to wait for next address.
116 mg82fg5b xx data sheet megawin 17.7. baud rate setting bits t2x12 (t2mod.4), t1x12 (auxr2.3) , urm0x 3 (s0cfg.5) and smod2 (s0cfg.6) provide a new option for the baud rate setting, as listed below. 17.7.1. baud rate in mode 0 mode 0 baud rate = n f sysclk ; n=12, if urm 0x3=0 ; n=4, if urm0x3=1 note : if urm0x 3 =0, the baud rate formula is as same as standard 8051. 17.7.2. baud rate in mode 2 mode 2 baud rate = 64 2 smod 1 x 2 ( smod 2 x 2 ) x f sysclk note : if smod2= 0, the baud rate formula is as same as standard 8051. if smod2=1, there is an enhanced function for baud rate setting. table 17? 1 defines the baud rate setting with smod2 factor in mode 2 baud rate generator. tabl e 17 ? 1 . smod2 application criteria in mode 2 smod2 smod1 baud rate note recommended max. receive error (%) 0 0 default baud rate standard function x2 enhanced function x4 enhanced function 17.7.3. baud rate in mode 1 & 3 16.7.3.1 using timer 1 as the baud rate generator mode 1, 3 baud rate = 32 x f sysclk 12 x (256 C th1) ; t1x12=0 or = 32 x ; t1x12=1 f sysclk 1 x (256 C th1) 2 smod1 x 2 (smod2 x 2) 2 smod1 x 2 (smod2 x 2) note : if smod2=0, t1x12=0, the baud rate formula is as same as standard 8051. if smod2=1, there i s an enhanced function for baud rate setting. table 17? 2 defines the baud rate setting with smod2 factor in timer 1 baud rate generator. table 17 ? 2 . smod2 applicatio n criteria in mode 1 & 3 using timer 1 smod2 smod1 baud rate note recommended max. receive error (%) 0 0 default baud rate standard function x2 enhanced function x4 enhanced function
megawin mg82fg5b xx data sheet 117 table 17 ? 3 ~ table 17 ? 10 list various commonly used baud rates and how they can be obtained from timer 1 in its 8 - bit auto - reload mode. t able 17 ? 3 . timer 1 generated commonly used baud rates @ f sysclk =11.0592mhz baud rate th1 , the reload value t1x12=0 & smod2=0 t1x12=1 & smod2=0 smod1=0 smod1=1 error smod1=0 smod1=1 error 1200 232 208 0.0% -- -- -- 2400 244 232 0.0% 112 -- 0.0% 4800 250 244 0.0% 184 112 0.0% 9600 253 250 0.0% 220 184 0.0% 14400 254 252 0.0% 232 208 0.0% 19200 -- 253 0.0% 238 220 0.0% 28800 255 254 0.0% 244 232 0.0% 38400 -- -- -- 247 238 0.0% 57600 -- 255 0.0% 250 2 44 0.0% 115200 -- -- -- 253 250 0.0% 230400 -- -- -- -- 253 0.0% table 17 ? 4 . timer 1 generated high baud rates @ f sysclk =11.0592mhz baud rate th1 , the reload value t1x12=0 & smod2=1 t1x12=1 & smod2=1 smod1=0 smod1=1 error smod 1 =0 smod 1 =1 error 230.4k -- 255 0.0% 250 244 0.0% 460.8k -- -- -- 253 250 0.0% 691.2k -- -- -- 254 252 0.0% 921.6k -- -- -- -- 253 0.0% 1.3824m -- -- -- 255 254 0.0% 2.7648m -- -- -- -- 255 0.0% table 17 ? 5 . timer 1 generated commonly used baud rates @ f sysclk = 22 . 1184 mhz baud rate th1 , the reload value t1x12=0 & smod2=0 t1x12=1 & smod2=0 smod1=0 smod1=1 error smod1=0 smod1=1 error 1200 208 160 0.0% -- -- -- 2400 232 208 0. 0% -- -- 0.0% 4800 244 232 0.0% 112 -- 0.0% 9600 250 244 0.0% 184 112 0.0% 14400 252 248 0.0% 208 160 0.0% 19200 253 250 0.0% 220 184 0.0% 28800 254 252 0.0% 232 208 0.0% 38400 -- 253 0.0% 238 220 0.0% 57600 255 254 0.0% 244 232 0.0% 115200 -- 255 0.0% 250 244 0.0% 230400 -- -- -- 253 250 0.0% 460800 -- -- -- -- 253 0.0% table 17 ? 6 . timer 1 generated high baud rates @ f sysclk = 22. 1184 mhz
118 mg82fg5b xx data sheet megawin baud rate th1 , the reload value t1x12=0 & smod2=1 t1x12=1 & s mod2=1 smod1=0 smod1=1 error smod 1 =0 smod 1 =1 error 460.8k -- 255 0.0% 250 244 0.0% 691.2k -- -- -- 252 248 0.0% 921.6k -- -- -- 253 250 0.0% 1.3824m -- -- -- 254 252 0.0% 1.8432m -- 253 0.0% 2.7648m -- -- -- 255 254 0.0% 5.5296m -- -- -- -- 255 0.0% table 17 ? 7 . timer 1 generated commonly used baud rates @ f sysclk =1 2 .0mhz baud rate th1 , the reload value t1x12=0 & smod2=0 t1x12=1 & smod2=0 smod 1 =0 smod 1 =1 error smod 1 =0 smod 1 =1 error 1200 230 204 0.16% -- -- -- 2400 243 230 0.16% 100 -- 0.16% 4800 -- 243 0.16% 178 100 0.16% 9600 -- -- -- 217 178 0.16% 14400 -- -- -- 230 204 0.16% 19200 -- -- -- -- 217 0.16% 28800 -- -- -- 243 230 0.16% 38400 -- -- -- 246 236 2.34% 57600 -- -- -- -- 243 0. 16% 115200 -- -- -- -- -- -- table 17 ? 8 . timer 1 generated high baud rates @ f sysclk =1 2 .0mhz baud rate th1 , the reload value t1x12=0 & smod2=1 t1x12=1 & smod2=1 smod1=0 smod1=1 error smod 1 =0 smod 1 =1 err or 115.2k -- -- -- 243 230 0.16% 230.4k -- -- -- -- 243 0.16% 460.8k -- -- -- -- -- --
megawin mg82fg5b xx data sheet 119 table 17 ? 9 . timer 1 generated commonly used baud rates @ f sysclk = 24 .0mhz baud rate th1 , the reload value t1x12=0 & smod2=0 t1x12=1 & smod2=0 smod 1 =0 smod 1 =1 error smod 1 =0 smod 1 =1 error 1200 204 152 0.16% -- -- -- 2400 230 204 0.16% -- -- -- 4800 243 230 0.16% 100 -- 0.16% 9600 -- 243 0.16% 178 100 0.16% 14400 -- -- -- 204 152 0.16% 19200 -- -- -- 217 178 0.16 % 28800 -- -- -- 230 204 0.16% 38400 -- -- -- -- 217 0.16% 57600 -- -- -- 243 230 0.16% 115200 -- -- -- -- 243 0.16% table 17 ? 10 . timer 1 generated high baud rates @ f sysclk = 24 .0mhz baud rate th1 , the re load value t1x12=0 & smod2=1 t1x12=1 & smod2=1 smod1=0 smod1=1 error smod 1 =0 smod 1 =1 error 230.4k -- -- -- 243 230 0.16% 460.8k -- -- -- -- 243 0.16% 691.2k -- -- -- -- -- -- 921.6k -- -- -- -- -- --
120 mg82fg5b xx data sheet megawin 16.7.3.2 using timer 2 as the baud rate generator wh en timer 2 is used as the baud rate generator (either tclk or rclk in t2con is ?1?), the baud rate is as follows. 2 smod2 x ( smod1 + 1) x f sysclk 32 x (65536 C (rcap2h, rcap2l)) mode 1, 3 baud rate = ; t2x12=0 or = ; t2x12=1 2 smod2 x ( smod1 + 1) x f sysclk 16 x (65536 C (rcap2h, rcap2l)) note : if smod2=0, the baud rate formula is as same as standard 8051. if smod2=1, there is an enhanced function for baud rate setting. table 17? 11 defines the baud rate setting with smod2 factor in timer 2 baud rate generator. table 17 ? 11 . smod2 application criteria in mode 1 & 3 using timer 2 smod2 smo d1 baud rate note recommended max. receive error (%) 0 x default baud rate standard function x2 enhanced function sysclk =11.0592mhz baud rate [rcap2h, rcap2l] , the reload value t2x12=0 & smod2=0 t2x12=1 & smod2=0 smod1=0 smod1=1 error smod1=0 smod1=1 error 1200 65248 65248 0.0% 64960 64960 0.0% 2400 65392 65392 0.0% 65248 65248 0.0% 4800 65464 65464 0.0% 65392 65392 0.0% 9600 65500 65500 0.0% 65464 65464 0.0% 14400 65512 65512 0.0% 65488 65488 0.0% 19200 65518 65518 0.0% 65500 65500 0.0% 28800 65524 65524 0.0% 65512 65512 0.0% 38400 65527 65527 0.0% 65518 65518 0.0% 57600 65530 65530 0.0% 65524 65524 0.0% 115200 65533 65533 0.0% 65530 65530 0.0% 230400 -- -- -- 65533 65533 0.0%
megawin mg82fg5b xx data sheet 121 table 17 ? 13 . timer 2 generated high baud rates @ f sysclk =11.0592mhz baud rate [rcap2h, rcap2l] , the reload value t2 x12=0 & smod2=1 t2x12=1 & smod2=1 smod1=0 smod1=1 error smod 1 =0 smod 1 =1 error 230.4k 65533 65530 0.0% 65530 65524 0.0% 460.8k -- 65533 0.0% 65533 65530 0.0% 691.2k 65535 65534 0.0% 65534 65532 0.0% 921.6k -- -- -- -- 65533 0.0% 1.3824m -- 65535 0.0% 65535 65534 0.0% 2.7648m -- -- -- -- 65535 0.0% table 17 ? 14 . timer 2 generated commonly used baud rates @ f sysclk = 22. 1184 mhz baud rate [rcap2h, rcap2l] , the reload value t2x12=0 & smod2=0 t2x12=1 & smod2 =0 smod1=0 smod1=1 error smod1=0 smod1=1 error 1200 64960 64960 0.0% 64384 64384 0.0% 2400 65248 65248 0.0% 64960 64960 0.0% 4800 65392 65392 0.0% 65248 65248 0.0% 9600 65464 65464 0.0% 65392 65392 0.0% 14400 65488 65488 0.0% 65440 65440 0.0% 19200 65500 65500 0.0% 65464 65464 0.0% 28800 65512 65512 0.0% 65488 65488 0.0% 38400 65518 65518 0.0% 65500 65500 0.0% 57600 65524 65524 0.0% 65512 65512 0.0% 115200 65530 65530 0.0% 65524 65524 0.0% 230400 65533 65533 0.0% 65530 65530 0.0% 460800 -- -- -- 65533 65533 0.0% table 17 ? 15 . timer 2 generated high baud rates @ f sysclk = 22. 1184 mhz baud rate [rcap2h, rcap2l] , the reload value t2x12=0 & smod2=1 t2x12=1 & smod2=1 smod1=0 smod1=1 error smod 1 =0 smod 1 =1 error 460.8k 65533 65530 0.0% 65530 65524 0.0% 691.2k 65534 65532 0.0% 65532 65528 0.0% 921.6k -- 65533 0.0% 65533 65530 0.0% 1.3824m 65535 65534 0.0% 65534 65532 0.0% 1.8432m -- -- -- -- 65533 0.0% 2.7648m -- 65535 0.0% 65535 65534 0.0% 5.5296m -- -- -- -- 65535 0.0%
122 mg82fg5b xx data sheet megawin table 17 ? 16 . timer 2 generated commonly used baud rates @ f sysclk =1 2 .0mhz baud rate [rcap2h, rcap2l] , the reload value t2x12=0 & smod2=0 t2x12=1 & smod2=0 smod 1 =0 smod 1 =1 error smod 1 =0 smod 1 =1 error 1200 65224 65224 0.16% 64912 64912 0.16% 2400 65380 65380 0.16% 65224 65224 0.16% 4800 65458 65458 0.16% 65380 65380 0.16% 9600 65497 65497 0.16% 65458 65458 0.16% 14400 65510 65510 0.16% 65484 65484 0.16% 19200 65516 65516 2.34 % 65497 65497 0.16% 28800 65523 65523 0.16% 65510 65510 0.16% 38400 -- -- -- 65516 65516 2.34% 57600 -- -- -- 65523 65523 0.16% 115200 -- -- -- -- -- -- table 17 ? 17 . timer 2 generated high baud rates @ f sysclk =1 2 .0mhz baud rate [rcap2h, rcap2l] , the reload value t2x12=0 & smod2=1 t2x12=1 & smod2=1 smod1=0 smod1=1 error smod 1 =0 smod 1 =1 error 115.2k -- 65523 0.16% 65523 65510 0.16% 230.4k -- -- -- -- 65523 0.16% 460.8k -- -- -- -- -- -- table 17 ? 18 . timer 2 generated commonly used baud rates @ f sysclk = 24 .0mhz baud rate [rcap2h, rcap2l] , the reload value t2x12=0 & smod2=0 t2x12=1 & smod2=0 smod 1 =0 smod 1 =1 error smod 1 =0 smod 1 =1 error 1200 64912 64912 0.16% 64288 64288 0.16% 2400 65224 65224 0.16% 64912 64912 0.16% 4800 65380 65380 0.16% 65224 65224 0.16% 9600 65458 65458 0.16% 65380 65380 0.16% 14400 65484 65484 0.16% 65432 65432 0.16% 19200 65497 65497 0.16% 65458 65458 0.16% 28800 65510 65510 0.16% 65484 65484 0.16% 38400 65516 65516 2.34% 65497 65497 0.16% 57600 65523 65523 0.16% 65510 65510 0.16% 115200 -- -- -- 65523 65523 0.16% table 17 ? 19 . timer 2 generated high baud rates @ f sysclk = 24 .0mhz baud rate [rcap2h, rcap2l] , the reload value t2x12=0 & smod2=1 t2x12=1 & smod2=1 smod1=0 smod1=1 error smod 1 =0 smod 1 =1 error 230.4k -- 65523 0.16% 65523 65510 0.16% 460.8k -- -- -- -- 65523 0.16% 691.2k -- -- -- -- -- -- 921.6k -- -- -- -- -- --
megawin mg82fg5b xx data sheet 123 16.7.3.3 using s1 baud rate timer as the baud rate generator the secondary uart (s1) in mg82fg5bxx has an independent baud - rate generator. s0 can set urts (s0cfg.7) to select the s1brt as the timer source for uart mode 1 and mode 3. see section ? 18.6 s1 baud rate generator (s1brg) for s0 ? for details for the s0 baud rate select.
124 mg82fg5b xx data sheet megawin 17.8. serial port 0 mode 4 (spi master) the serial port of mg82fg5bxx is embedded an additional mode 4 to support spi master engine. the mode 4 is selected by sm30, sm00 and sm10. table 17 ? 20 shows the serial port mode definition in mg82fg5bxx . table 17 ? 20 . serial po rt 0 mode selection sm30 sm00 sm10 mode description baud rate 0 0 0 0 shift register sysclk/12 or sysclk/4 0 0 1 1 8 - bit uart variable 0 1 0 2 9 - bit uart sysclk/64, /32 0 1 1 3 9 - bit uart variable 1 0 0 4 spi master sysclk/12 or sysclk/4 1 0 1 5 rese rved reserved 1 1 0 6 reserved reserved 1 1 1 7 reserved reserved urm0x3 also control s the spi transfer speed. if urm0x3 = 0, the spi clock frequency is sysclk/12. if urm0x3 = 1, the spi clock frequency is sysclk/4. the spi master in mg82fg5bxx uses t he txd0 as spiclk, rxd0 as mosi, and s0mi as miso. nss is selected by mcu software on other port pin. figure 17 ? 10 shows the spi connection. it also can support the configuration for multiple slaves communication i n figure 17 ? 11 . figure 17? 10. serial port 0 mode 4, single master and single slave configuration (n = 0) mode 4 ( master) spi slave snmi rxdn txdn port pin miso mosi spiclk nss mcu serial port n figure 17? 11. serial port 0 mode 4, single master and multiple slaves configuration (n = 0) mode 4 ( master ) slave # 1 snmi rxdn txdn port pin 1 miso mosi spiclk nss slave #2 miso port pin 2 nss spiclk mosi mcu serial port n
megawin mg82fg5b xx data sheet 125 the spi master satisfies the transfer with the full function spi module of megawin mg82/84 series mcu with cpol, cpha and dord selection. for cpol and cpha condit ion, mg82fg5bxx uses an easy way by initialize spi clock assigned port pin (txd 0, p3.1 /p4.5 ) polarity to fit them . table 17? 21 shows the serial port mode 4 mapping with the four spi operating mode. table 17 ? 21 . spi mode mapping with serial port 0 mode 4 configuration spi mode cpol cpha configuration in mg82fg5bxx when txd0 on p3.1 0 0 0 clear p3.1 to ? 0 ? 1 0 1 clear p3.1 to ? 0 ? 2 1 0 set p3.1 to ? 1 ? 3 1 1 set p3.1 to ? 1 ? for bit order control (dord) on spi serial transfer, mg82fg5bxx provides a sfr, borev, to reverse the bit order by software program. after mcu writing a msb first data format to borev, mcu will get the lsb first data by reading borev back. the spi master engine in serial port 0 mode 4 is the lsb first transferred which is same as serial port 0 mode 0. to support spi msb first shift, mcu must use the borev write/read operation to reverse the data bit order for spi in/out transmission. figure 17 ? 12 shows the borev configuration. figure 17? 12. sfr borev read/write configuration d0 d1 d2 d3 d4 d5 d6 d7 borev mcu write d0 d1 d2 d3 d4 d5 d6 d7 mcu read transmission is initiated by any instruction that uses s 0 buf as a destination re gister. the ? write to s0buf ? signal triggers the uart engine to start the transmission. the data in the s0buf would be shifted o nto the rxd0 pin as mosi serial data. t he spi shift clock is built on the txd0 pin for spiclk output. after eight raising edge o f shift clocks passing, ti 0 would be asserted by hardware to indicate the end of transmission. a nd the contents on the s0mi pin would be sampled and shifted into shift register. then, ? read s0buf ? can get the spi shift - in data. figure 17? 13 shows the transmission waveform in mode 0. ri 0 will not be asserted in mode 4. figure 17? 13. serial port 0 mode 4 transmission waveform (n = 0) write to snbuf txdn (spiclk) rxdn (mosi) tin rin d0 d1 d2 d3 d4 d5 d6 d7 software set/clear txdn assigned port pin to initial clock polarity d0 d1 d2 d3 d4 d5 d6 d7 snmi (miso)
126 mg82fg5b xx data sheet megawin 17.9. serial port 0 register all the four operation modes of the serial port are the same as those of the standard 8051 except the baud rate setting. three registers, pcon, auxr 2 and s0cfg , are related to the baud rate setting: s0con: serial port 0 control register sfr page = 0 only sfr address = 0x98 reset = 0000 - 0000 7 6 5 4 3 2 1 0 sm00/fe sm10 sm20 ren0 tb80 rb80 ti0 ri0 r/w r/w r/w r/w r/w r/w r/w r/w bit 7: fe, framing error bit . the smod0 bit must be set to enable access to the fe bit . 0: the fe bit is not cleared by valid f rames but should be cleared by software. 1: this bit is set by the receiver when an invalid stop bit is detected. bit 7: serial port 0 mode bit 0, (smod0 must = 0 to access bit sm00) bit 6: serial port 0 mode bit 1. sm30 sm00 sm10 mode description baud r ate 0 0 0 0 shift register sysclk/12 or sysclk/4 0 0 1 1 8 - bit uart variable 0 1 0 2 9 - bit uart sysclk/64, /32, /16 or /8 0 1 1 3 9 - bit uart variable 1 0 0 4 spi master sysclk/12 or sysclk/4 1 0 1 5 reserved reserved 1 1 0 6 reserved reserved 1 1 1 7 reserved reserved bit 5: serial port 0 mode bit 2. 0: disable sm20 function. 1: enable the automatic address recognition feature in m ode s 2 and 3. if sm2 0 =1, ri 0 will not be set unless the received 9th data bit is 1, indicating an address, and the rec eived byte is a given or broadcast address. in mode1, if sm2 0 =1 then ri 0 will not be set unless a valid stop bit was received, and the received byte is a given or broadcast address. in mode 0, sm20 should be 0. bit 4: ren0, enable serial reception. 0: cle ar by software to disable reception. 1: set by software to enable reception. bit 3: tb80, the 9 th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. bit 2: rb80, in modes 2 and 3, the 9 th data bit that was received. in mode 1, if sm20 = 0, rb80 is the stop bit that was received. in mode 0, rb80 is not used. bit 1: ti0. transmit interrupt flag. 0: must be cleared by software. 1: set by hardware at the end of the 8 th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. bit 0: ri0. receive interrupt flag. 0: must be cleared by software. 1: set by hardware at the end of the 8 th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial rec eption (except see sm20).
megawin mg82fg5b xx data sheet 127 s0buf: serial port 0 buffer register sfr page = 0 only sfr address = 0x99 reset = xxxx - xxxx 7 6 5 4 3 2 1 0 s0buf.7 s0buf.6 s0buf.5 s0buf.4 s0buf.3 s0buf.2 s0buf.1 s0buf.0 r/w r/w r/w r/w r/w r/w r/w r/w bit 7~0: it is u sed as the buffer register in transmission and reception. saddr: slave address register sfr page = 0~f sfr address = 0xa9 reset = 0000 - 0000 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w saden: slave address mask register sfr page = 0~f sfr address = 0xb9 reset = 0000 - 0000 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w saddr register is combined with saden register to form given/broadcast address for automatic address recognition. in fact, saden functions as the ?mask? reg ister for saddr register. the following is the example for it. saddr = 1100 0000 saden = 1111 1101 given = 1100 00x0 the given slave address will be checked ex cept bit 1 is treated as ?don?t care? the broadcast address for each slave is create d by taking the logical or of saddr and saden. zero in this result is considered a s ?don?t care?. upon reset, saddr and saden are loaded with all 0s. this produces a given address of all ?don?t care? and a broadcast address of all ?don?t care?. this disables the automatic address detection feature. pcon0: power control register 0 sfr page = 0~f sfr address = 0x87 por = 00x1 - 0000, reset = 00 0 0 - 0000 7 6 5 4 3 2 1 0 smod1 smod0 gf pof gf1 gf0 pd idl r/w r/w r/ w r/w r/w r/w r/w r/w bit 7: smod 1 , double baud rate control bit. 0: disable double baud rate of the uart. 1: enable double baud rate of the uart in mode 1, 2, or 3. b it 6: smod0, frame error select. 0: s0con.7 is sm0 function. 1: s0con.7 is fe function. note that fe will be set after a frame error regardless of the state of smod0.
128 mg82fg5b xx data sheet megawin s0cfg: serial port 0 configuration registe r sfr page = 0 only sfr address = 0x9 c reset = 0000 - 1 00x 7 6 5 4 3 2 1 0 urts smod2 urm0x3 sm30 s0dor bti utie -- r/w r/w r/w r/ w r/ w r/ w r/ w w bit 7: urts, uart0 timer selection. 0: timer 1 or timer 2 can be used as the baud rate generator in mode 1 and mode 3. 1: timer 1 overflow signal is replaced by the uart 1 baud rate timer overflow signal when timer 1 is selected as the baud rate generator in mode1 or mode 3 of the uart 0 . (refer section ? 17.7.3 baud rate in mode 1 & 3 ? .) bit 6 : smod2, uart0 extra double baud rate selector. 0: disable extra double baud rate for uart0 . 1: enable extra double baud rate for uart0 . bit 5: urm0x 3, serial port mode 0 and mode 4 bau d rate select or . 0: clear to select sysclk/12 as the baud rate for uart mode 0 and mode 4. 1: set to select sysclk/4 as the baud rate for uart mode 0 and mode 4. bit 4: sm3 0 , serial port mode control bit 3. 0: disable serial prot mode 4. 1: enable sm30 to control serial port mode 4, spi master. refer s0con description for more s0 mode selecting information. bit 3: s0 dor , serial port 0 data order control in mode 4. 0: the msb of the data byte is transmitted first. 1: the lsb of the data byte is transmitted first. s0dor is set to ? 1 ? in default. bit 2: bti, block ti0 in serial port 0 interrupt. 0: retain the ti0 to be a source of serial port 0 interrupt . 1: block ti0 to be a source of serial port 0 interrupt . bit 1 : utie, s0 ti 0 enabled in system flag inte rrupt. 0: disable the interrupt vector sharing for ti0 in system flag interrupt. 1: set ti0 flag will share the interrupt vector with system flag interrupt. bit 0 : reserved. software must write ? 0 ? on this bit when s0cfg is written. auxr2: auxiliary reg ister 2 sfr page = 0~f sfr address = 0xa3 reset = 0000 - 0000 7 6 5 4 3 2 1 0 int3is1 int3is0 int2is1 int2is0 t1x12 t0x12 t1ckoe t0ckoe r/w r/w r/w r/w r/w r/w r/w r/w bit 3: t1x12 , timer 1 clock sour ce select or while c/t=0. 0: c lear to select sysclk /12. 1: set to select sysclk as the clock source . if set, the uart0 baud rate by timer 1 in mode 1 and mode 3 is 12 times than standard 8051 function.
megawin mg82fg5b xx data sheet 129 18. serial port 1 (uart1) the mg82fg5bxx is equipped with a secondary uart (hereafter, called uart 1 ), whic h also has 5 operation modes the same as the first uart (uart0) except the following differences: (1) the uart 1 has no enhanced functions: framing error detection and auto address recognition. (2) the uart 1 use the dedicated baud rate timer as its baud ra te generator (s1brg) . (3) the uart 1 uses t xd 1 (p1.3/p3.4 ) and rxd 1 (p1.2/p3.3 ) for transmit and receive, respectively. (4) the baud rate generator provide the toggle source for s1cko and peripheral clock. (5) s1 + s1brg can be configured to an 8 - bit auto - r eload timer with port change detection. (6) in mode 0 and mode 4, s1tx12 of uart1 is the same function as urm0x3 in uart0. the uart 1 and uart0 in mg82fg5bxx can operate simultaneously in identical or different modes and communication speeds. 18.1. serial port 1 baud rate generator (s1brg) the mg82fg5bxx has an embedded baud rate generator to generate the uart clock for serial port 1 operation in mode 1 and mode 3. it is constructed by a n 8 - bit up- counter, s1brc, and a n 8 - bit reload register, s1brt. the o verflo w of s1brc, s1tof, is the time base of uart1 serial engine in mode 1 and mode 3 and triggers the s1brt content reloaded into s1brc for the consecutive counting . this baud rate generator can also provide the time base for serial port 0 by software configur ed. there is an addition clock output, s1cko, from the s1br c overflow rate by 2 (s1tof/2). s1tof also supplies the toggle source for uart0, pca, spi, twi 0 , twi1 and adc clock input. regardless s1 engine is running or pending, s1brg always serves the time b ase function for these peripherals. the configuration of the serial port 1 baud rate generator is shown in figure 18 ? 1 . figure 18? 1 . s1brg configuration (s1tme=0) s 1 tr ( s 1 cfg . 4 ) s 1 brt ( 8 bits) s1brc (8 bits) reload sysclk /12 sysclk 0 1 overflow tx clock rx clock uart1 (s1 ) mode1 and mode3 ti1 ri1 uart1 (s1) interrupt s1tx12 ( s1cfg.2 ) s1brc overflow (s1tof) 1. to s1cko 2. to peripheral clock
130 mg82fg5b xx data sheet megawin 18.2. serial port 1 baud rate setting 18.2.1. baud rate in mode 0 s1 mode 0 baud rate = n f sysclk ; n=12, if s1t x12=0 ; n=4, if s1 tx12=1 18.2.2. baud rate in mode 2 s 1 mode 2 baud rate = 64 2 s 1 mod1 x f sysclk 18.2.3. baud rate in mode 1 & 3 s 1 mode 1, 3 baud rate = 32 x 12 x (256 C s1brt) ; s1tx12=0 or = 32 x ; s1tx12=1 1 x (256 C s1brt) 2 s1mod1 2 s1mod1 f sysclk f sysclk table 1 7 - 1 ~ table 1 7 - 4 list various commonly used baud rates and how they can be obtained from s1brg, serial port 1 baud rate generato r. table 18 ? 1 . s1brg generated commonly used baud rates @ f sysclk =11.0592mhz baud rate s1brt , reload value of s1brg s1tx12=0 s1tx12=1 s1mod1=0 s1mod1=1 error s1mod1=0 s1mod1=1 error 1200 232 208 0.0% -- -- -- 2400 244 232 0.0% 112 -- 0.0% 4800 250 244 0.0% 184 112 0.0% 9600 253 250 0.0% 220 184 0.0% 14400 254 252 0.0% 232 208 0.0% 19200 -- 253 0.0% 238 220 0.0% 28800 255 254 0.0% 244 232 0.0% 38400 -- -- -- 247 238 0.0% 57600 -- 255 0.0% 250 244 0.0% 115200 -- -- -- 253 250 0.0% 230400 -- -- -- -- 253 0.0% table 18 ? 2 . s1brg generated commonly used baud rates @ f sysclk = 22 . 1184 mhz baud rate s1brt , r eload value of s1brg s1tx12=0 s1tx12=1 s1mod1= 0 s1mod1=1 error s1mod1=0 s1mod1=1 error 1200 208 160 0.0% -- -- -- 2400 232 208 0.0% -- -- 0.0% 4800 244 232 0.0% 112 -- 0.0%
megawin mg82fg5b xx data sheet 131 9600 250 244 0.0% 184 112 0.0% 14400 252 248 0.0% 208 160 0.0% 19200 253 250 0.0% 220 184 0.0% 28800 254 252 0.0% 232 208 0.0% 38400 -- 253 0.0% 238 220 0.0% 57600 255 254 0.0% 244 232 0.0% 115200 -- 255 0.0% 250 244 0.0% 230400 -- -- -- 253 250 0.0% 460800 -- -- -- -- 253 0.0% table 18 ? 3 . s1brg generated commonly used ba ud rates @ f sysclk =1 2 .0mhz baud rate s1brt , reload value of s1brg s1tx12=0 s1tx12=1 s1mod1=0 s1mod1=1 error s1mod1=0 s1mod1=1 error 1200 230 204 0.16% -- -- -- 2400 243 230 0.16% 100 -- 0.16% 4800 -- 243 0.16% 178 100 0.16% 9600 -- -- -- 217 178 0. 16% 14400 -- -- -- 230 204 0.16% 19200 -- -- -- -- 217 0.16% 28800 -- -- -- 243 230 0.16% 38400 -- -- -- 246 236 2.34% 57600 -- -- -- -- 243 0.16% 115200 -- -- -- -- -- -- table 18 ? 4 . s1brg generated commonly used baud rates @ f sysclk = 24 .0mhz baud rate s1brt , reload value of s1brg s1tx12=0 s1tx12=1 s1mod1=0 s1mod1=1 error s1mod1=0 s1mod1=1 error 1200 204 152 0.16% -- -- -- 2400 230 204 0.16% -- -- -- 4800 243 230 0.16% 100 -- 0.16% 9600 -- 243 0.16% 178 100 0.16% 14400 -- -- -- 204 152 0.16% 19200 -- -- -- 217 178 0.16% 28800 -- -- -- 230 204 0.16% 38400 -- -- -- -- 217 0.16% 57600 -- -- -- 243 230 0.16% 115200 -- -- -- -- 243 0.16%
132 mg82fg5b xx data sheet megawin 18.3. serial port 1 mode 4 (spi master) the serial port of mg82fg5bxx is embedded mode 4 to support spi master engine. the mode 4 is selected by sm3 1 , sm0 1 and sm1 1 . table 18 ? 5 shows the serial port mode definition in mg82fg5bxx . table 18 ? 5 . serial port 1 mode selection sm31 sm0 1 sm1 1 mode description baud rate 0 0 0 0 shift register sysclk/12 or sysclk/4 0 0 1 1 8 - bit uart variable 0 1 0 2 9 - bit uart sysclk/64, /32 0 1 1 3 9 - bit uart variable 1 0 0 4 spi master sysclk/1 2 or sysclk/4 1 0 1 5 reserved reserved 1 1 0 6 reserved reserved 1 1 1 7 reserved reserved s1tx12 also control s the spi transfer speed. if s1tx12 = 1 , the spi clock frequency is sysclk/ 4 . otherwise, the spi clock frequency is sysclk/ 12 . the spi mas ter in mg82fg5bxx uses the txd 1 as spiclk, rxd 1 as mosi, and s 1 mi as miso. nss is selected by mcu software on other port pin. figure 18 ? 2 shows the spi connection. it also can support the configuration for multiple slaves communication in figure 18 ? 3 . figure 18? 2 . serial port mode 4, single master and single slave configuration (n = 1) mode 4 ( master) spi slave snmi rxdn txdn port pin miso mosi spiclk nss mcu serial port n figure 18? 3 . serial port mode 4, single master and multiple slaves configuration (n = 1) mode 4 ( master ) slave # 1 snmi rxdn txdn port pin 1 miso mosi spiclk nss slave #2 miso port pin 2 nss spiclk mosi mcu serial port n
megawin mg82fg5b xx data sheet 133 the spi master satisfies the transfer with the full function spi module of megawin mg82/84 series mcu with cpol, cpha and dord selection. for cpol and cpha condition, mg82fg5bxx uses an easy way by initialize spi clock assigned port pin (txd 1, p1 .3/p3.4 ) polarity to fit them . table 17? 21 shows the serial port mode 4 mapping with the four spi operating mode. table 18 ? 6 . spi mode mapping with serial port mode 4 configuration spi mode cpol cpha configuration in mg82fg5bxx when txd1 on p1.3 0 0 0 clear p 1 . 3 to ? 0 ? 1 0 1 clear p 1 . 3 to ? 0 ? 2 1 0 set p 1 . 3 to ? 1 ? 3 1 1 set p 1 . 3 to ? 1 ? for bit order control (dord) on spi serial transfer, mg82fg5bxx provides a sfr, borev, to reverse the bit order by software program. after mcu writing a msb first data format to borev, mcu will get the lsb first data by reading borev back. the spi master engine in serial port 1 mode 4 is the lsb first transferred which is same as serial port 1 mode 0. to support spi msb first shift, mcu must use the borev write/read operation to reverse the data bit order for spi in/out transmission. figure 18 ? 4 shows the borev configuration. figure 18? 4 . sfr borev read/write configuration d0 d1 d2 d3 d4 d5 d6 d7 borev mcu write d0 d1 d2 d3 d4 d5 d6 d7 mcu read transmission is initiated by any instruction that uses s 1 buf as a des tination register. the ? write to s 1 buf ? signal triggers the uart engine to start the transmission. the data in the s 1 buf would be shifted on to the rxd 1 pin as mosi serial data. t he spi shift clock is built on the txd 1 pin for spiclk output. after eight rai sing edge of shift clocks passing, ti 1 would be asserted by hardware to indicate the end of transmission. a nd the contents on the s 1 mi pin would be sampled and shifted into shift register. then, ? read s 1 buf ? can get the spi shift - in data. figure 18? 5 shows the transmission waveform in mode 0. ri 1 will not be asserted in mode 4. figure 18? 5 . serial port mode 4 transmission waveform (n = 1) write to snbuf txdn (spiclk) rxdn (mosi) tin rin d0 d1 d2 d3 d4 d5 d6 d7 software set/clear txdn assigned port pin to initial clock polarity d0 d1 d2 d3 d4 d5 d6 d7 snmi (miso)
134 mg82fg5b xx data sheet megawin 18.4. pure timer mode of s1 brg if the uart1 is not necessary in application or pending by software, setting s1tme=1 in the mg82fg5bxx provides the pure timer operating mode on s1 baud rate generator (s1brg). this timer operates as an 8 - bit auto - reload timer and provides the overflo w flag which is set on the ti1 ( s1con.1 ) . the ri1 ( s1con.0 ) serves the port change detector on rxd1 port pin. both of ti1 and ri1 in this mode keep the interrupt capability on u art1 interrupt resource and have the individual interrupt enabled control (tb81 & ren1). rb81 selects the ri1 detection level on rxd1 port input. i f rb81=0, ri1 will be set by ren1=1 and rxd1 pin falling edge detecting. otherwise, ri1 will detect the rising edge on rxd1 port pin. in mcu power - down mode, the ri1 is forced to level - sen sitive operation and has the capability to wake up cpu if uart1 interrupt is enabled. this pure timer mode has a clock input option from timer 1 overflow which is a cascaded counter to perform a 16- bit timer. when s1brc overflows, it can be the clock sour ce of uart0, pca, adc, spi, twi 0 and twi1 or toggle the port pin output. ? s1ckoe=1 ? enables the s1cko output on port pin and masks the ri1 interrupt. the configuration of the pure timer mode of s1brg is shown in fi gure 18? 6 . figure 18? 6 . timer mode configuration for s1brg (s1tme=1) ren 1 ( s 1 con .4 ) transition detection ri1 rxd1 pin 0 1 s1brt (8 bits) s1brc (8 bits) reload sysclk /12 sysclk s1tx12 ( s1cfg.2 ) 0 1 overflow uart1 (s1) interrupt ti1 tb81 ( s1con.3 ) s1tr ( s1cfg.4 ) rb81 ( s1con.2 ) ( s1con.0 ) ( s1con.1 ) 0 1 sm21 ( s1con.5 ) timer 1 overflow s1brc overflow (s1tof ) 1. to s1cko 2. to peripheral clock
megawin mg82fg5b xx data sheet 135 18.5. s1brt programmable clock output when s1brc overflows, the overflow flag, s1tof, provides the toggle source for s1cko and periphe ral clock. the input clock (sysclk/12 or sysclk) increases the 8 - bit timer , s1brc. the timer repeatedly counts to overflow from a loaded value. once overflows occur, the content of s1brt is loaded into s1brc for the consecutive counting. figure 18 ? 7 shows the block diagram for the clock output mode of s1 baud rate generator. the following formula gives the clock - out frequency. sysclk frequency n x ( 256 C s 1 brt ) s 1 t clock - out frequency = ; n =24, if s1tx12=0 ; n=2, if s1tx12=1 note: ( 1 ) for sysclk=12mhz & s1tx12=0 , s1brg has a programmable output frequency rang e from 1.95k hz to 500k hz. ( 2 ) for sysclk=12mhz & s1tx12=1 , s1brg has a programmable output frequency range from 23.43k hz to 6 mhz. figure 18? 7 . s1brg in clock output mode s 1 brc overflow (s1tof) 1. to peripheral clock s1ckoe ( s1cfg.1 ) port latch toggle s1brt (8 bits) s1brc (8 bits) reload overflow s1tr ( s1cfg.4 ) sysclk /12 sysclk s1tx12 ( s1cfg.2 ) 0 1 0 1 sm21 (s1con.5) timer 1 overflow q s1cko d q 0 1 how to program 8 - bit s1brg in c lock - out mode ? select s1cfg.s1tx12 bit and s1con.sm21 bit to decide the s1brg clock source. ? determine the 8 - bit reload value from the formula and enter it in the s1brt and s1brc registers. ? set s1ck oe bit in s1cfg regi ster. ? set s1tr to start the s1b rc timer.
136 mg82fg5b xx data sheet megawin 18.6. s1 baud rate generator (s1brg) for s0 in the mode 1 and mode 3 operation of the uart 0 , the software can select timer 1 as the baud rate generator by clearing bits tclk and rclk in t2con register. at this time, if urts bit ( s0cfg .7 ) is set, th en timer 1 overflow signal will be replaced by the overflow signal of the uart 1 baud rate generator (s1brg) . in othe r words, the user can adopt s1brg as the baud rate generator for mode 1 or mode 3 of the uart 0 as long as rclk=0, tclk=0 and urts=1. in this condition, timer 1 is free for other application. of course, if uart 1 (mode 1 or mode 3) is also operated at this time, these two uarts will have the same baud rates. figure 18? 8 . additional baud rate sourc e for the uart0 tx clock rx clock timer 2 overflow uart0 mode1 and mode3 2 timer 1 overflow urts ( s0cfg.7 ) 0 1 s1brg overflow (s1tof) 0 1 smod1 ( pcon0.7 ) 0 1 0 1 tclk ( t2con.4 ) rclk ( t2con.5 )
megawin mg82fg5b xx data sheet 137 18.7. serial port 1 register the following special function registers are related to the operation of the uart 1 : s1con: serial port 1 control register sfr page = 1 only sfr address = 0x98 reset = 0000 - 0000 7 6 5 4 3 2 1 0 sm01 sm11 sm21 ren1 tb81 rb81 ti1 ri1 r/w r/w r/w r/w r/w r/w r/w r/w bit 7: sm01, serial port 1 mode bit 0. bit 6: sm11, serial port 1 mode bit 1. sm31 sm01 sm11 mode description baud rate 0 0 0 0 shift register sysclk/12 or sysclk/4 0 0 1 1 8 - bit uart v ariab le 0 1 0 2 9 - bit uart sysclk/64 or syscklk/32 0 1 1 3 9 - bit uart v ariable 1 0 0 4 spi master sysclk/12 or sysclk/4 1 0 1 5 reserved reserved 1 1 0 6 reserved reserved 1 1 1 7 reserved reserved bit 5: serial port 0 mode bit 2. 0: disable sm21 functi on. 1: enable the automatic address recognition feature in m ode s 2 and 3. if sm2 1 =1, ri 1 will not be set unless the received 9th data bit is 1, indicating an address, and the received byte is a given or broadcast address. in mode1, if sm2 1 =1 then ri 1 will not be set unless a valid stop bit was received, and the received byte is a given or broadcast address. in mode 0, sm21 should be 0. bit 4: ren1, enable serial reception. 0: clear by software to disable reception. 1: set by software to enable reception. bit 3: tb81, the 9 th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. bit 2: rb81, in modes 2 and 3, the 9 th data bit that was received. in mode 1, if sm21 = 0, rb81 is the stop bit that was received. in mode 0, rb8 1 is not used. bit 1: ti1. transmit interrupt flag. 0: must be cleared by software. 1: set by hardware at the end of the 8 th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. bit 0: ri1. receive inter rupt flag. 0: must be cleared by software. 1: set by hardware at the end of the 8 th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see sm21). s1buf: serial port 1 buffer register sfr page = 1 only sfr address = 0x99 reset = xxxx - xxxx 7 6 5 4 3 2 1 0 s1buf.7 s1buf.6 s1buf.5 s1buf.4 s1buf.3 s1buf.2 s1buf.1 s1buf.0 r/w r/w r/w r/w r/w r/w r/w r/w bit 7~0: it is used as the buffer register in transmission and reception.
138 mg82fg5b xx data sheet megawin s1brt: serial po rt 1 baud rate timer reload register sfr page = 1 only sfr address = 0x9a reset = 0000 - 0000 7 6 5 4 3 2 1 0 s1brt . 7 s1brt . 6 s1brt . 5 s1brt . 4 s1brt . 3 s1brt . 2 s1brt . 1 s1brt . 0 r/w r/w r/w r/w r/w r/w r/w r/w bit 7~0: it is used as the reload value regis ter for baud rate timer generator that works in a similar manner as timer 1 . s1brc: serial port 1 baud rate counter register sfr page = 1 only sfr address = 0x9b reset = 0000 - 0000 7 6 5 4 3 2 1 0 s1brc .7 s1brc . 6 s1brc . 5 s1brc . 4 s1brc . 3 s1brc . 2 s1brc . 1 s1brc . 0 r/w r/w r/w r/w r/w r/w r/w r/w bit 7~0: it is used as the reload value register for baud rate timer generator that works in a similar manner as timer 1 . this register can be always read/written by software. if s1cfg .s1tme = 0, software writin g s1brt will store the data content to s1brt and s1brc concurrently. s1cfg: serial port 1 configuration register sfr page = 0 only sfr address = 0x9 c reset = 001 0 - 0000 7 6 5 4 3 2 1 0 sm31 0 1 s1tr s1mod1 s1tx12 s1ckoe s1tme r/ w r/ w r/ w r/w r/w r/w r/ w r/ w bit 7: sm31, serial port 1 mode control bit 3. refer to s1con description. bit 6 ~5 : reserved. software must write ? 0 1 ? on these bits when s1cfg is written. bit 4: s 1 tr , uart 1 baud rate generator control bit. 0: clear to turn off the s1br g . 1: s et to turn on s1br g . bit 3: s 1 mod 1, uart 1 double baud rate enable bit. 0: disable the double baud rate function for uart1. 1: enable the double baud rate function for uart1. bit 2: s 1 tx12 , uart 1 baud rate generator clock source select 0: c lear to select sysclk /12 as the clock source for s1br g . 1: set to select sysclk as the clock source for s1br g . bit 1: s1ckoe, serial port 1 br g clock output enable. 0: disable the s1cko output on the port pin. 1: enable t he s1cko output on the port pin. bit 0: s1tme, s erial port 1 br g timer mode enabled. 0: keep s1br g to service serial port 1 (uart1). 1: disable serial port 1 function and release the s1br g as an 8- bit auto - reload timer. in this mode, there is an additional function for rxd1 port pin change detector.
megawin mg82fg5b xx data sheet 139 auxr1 : auxiliary control register 1 sfr page = 0~f sfr address = 0xa2 reset = 0000 - 0000 7 6 5 4 3 2 1 0 p1kbih p3kbil p4spi p3s1 p3s1mi p6twi p3cex dps r/w r/w r/w r/w r /w r /w r /w r/w bit 4: p3s1, serial port 1 (uart1) function on p3.3 and p3.4 if p 3cex (auxr1.1) is disabled. p3s1 rxd1 txd1 0 p1.2 p1.3 1 p3.3 p3.4 bit 3: p3s1mi, s1mi function on p 3 . 5 . s1mi is the spi serial data input of the s1 mode 4 (spi master). p3s1mi s1mi 0 p1.0 1 p3.5
140 mg82fg5b xx data sheet megawin 18.8. serial port sample code ( 1 ). required function: i dle mode with ri wake - up capability assembly code example: org 00023h uart_ri_idle_isr: jb ri,ri_isr ; jb ti,ti_isr ; reti ; ri_isr: ; proc ess clr ri ; reti ; ti_isr: ; process clr ti ; reti ; main : clr ti ; clr ri ; setb sm1 ; setb ren ; 8bit mode2, recei v e enable mov ip0l,#psl ; select s0 interrupt priority mov ip0h,#psh ; setb es ; enable s0 interrupt setb ea ; enable global interrupt orl pcon0,#idl; ; set mcu into idle mode c code example : void uart_ri_idle_isr(void) interrupt 4 { if(ri) { ri=0; // to do ... } if(ti) { ti=0; // to do ... } } void main (void) { ti = ri = 0; sm1 = ren = 1; // 8bi t mode2, recei v e enable ip0l = psl; / / select s0 interrupt priority ip0h = psh; / / es = 1; / / enable s0 interrupt ea = 1; / / enable global interrupt pcon |= idl; // set mcu into idle mode }
megawin mg82fg5b xx data sheet 141 19. programmable counter array (pca) the mg82fg5bxx is equipped with a programmable counter array (pca), which provides more timing capabilitie s with less cpu intervention than the standard timer/counters. its advantages include reduced software overhead and improved accuracy. 19.1. pca overview the pca consists of a dedicated timer/counter which serves as the time base for an array of 8 compare/capt ure modules. figure 19 ? 1 shows a block diagram of the pca. notice that the pca timer and modules are all 16 - bits. if an external event is associated with a module, that function is shared with the corresponding por t 2 p in . if the module is not using the port pin, the pin can still be used for standard i/o. m odule 0~5 can be programmed in any one of the following modes: - rising and/or falling edge capture - software timer - high speed output - pulse width modulato r (pwm) output module 6 and module 7 only support pwm output mode. all of these modes will be discussed later in detail. however, let's first look at how to set up the pca timer and modules. figure 19? 1 . p ca block diagram pca timer/counter 16 bits module 0 module 1 module 2 module 3 module 4 module 5 cex0 (p2.2)(p2.0)(p2.1) 16 bits each cex1 (p2.3/p3.3) cex2 (p2.4)(p4.0)(p4.1) cex3 (p2.5/p3.4) cex4 (p2.6)(p4.7) cex5 (p2.7/p3.5) 16 bits reload resigter overflow reload module 6 module 7 pwm6 (p2.0) pwm7 (p2.1)
142 mg82fg5b xx data sheet megawin 19.2. pca timer/counter the timer/counter for the pca is a n auto - reload 16 - bit timer consisting of registers ch and cl (the high and low bytes of the count values), chrl, clrl (the high and low bytes reload registers), as shown in figure 19 ? 2 . chrl and clrl are reload ed to ch and cl at each time overflow on { ch + cl } counter which can change the pca cycle time for variable pwm resolution, such as 7 - bit or 9 - bit pwm. {ch + cl} is the common time base for all modules and its clock input can be selected from the following source: - 1/12 the system clock frequency, - 1/2 the system clock frequency, - the timer 0 overflow, which allows for a range of slower clock inputs to the timer. - external clock input, 1 - to - 0 transitions, on eci pin ( p 2 .1 /p3.2 ). special function register cmod contains the count pulse select bits ( cps2, cps1 and cps0) to specify the pca timer input. this register also contains the ecf bit which enables an interrupt when the coun ter overflows. in addition, the user has the option of turning off the pca timer during idle mode by setting the counter idle bit (cidl). this can further reduce power consumption during idle mode. figure 19? 2 . pca timer/counter external input eci (p2.1 ) timer0 overflow sysclk/2 sysclk/12 ch 8 bits cl 8 bits 16-bits up counter to pca module 0~5 ecf cps0 cps1 cps2 bme0 bme2 bme4 cidl ccf0 ccf1 ccf2 ccf3 ccf4 ccf5 cr cf idle cmod ccon control clrl chrl overflow pca interrupt enable cf reload (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0 ,1) (1,1 ,0) (1,1,1) sysclk s1brg overflow mckdo cps[2:0] indexed ckmix16 cmod: pca counter mode register sfr page = 0~f sfr address = 0xd9 reset = 00 00- 0 000 7 6 5 4 3 2 1 0 cidl bme4 bme2 bme0 cps2 cps1 cps0 ecf r/w r/w r/ w r/ w r/ w r/w r/w r/w bit 7: cidl , pca counter idle control. 0 : l ets th e pca counter continue functioning during idle mode. 1 : l ets the pca counter be gated off during idle mode. bit 6 ~4 : bme4/2/0. reserved for test mode. software must write ? 0 ? on this bit when the cmod is written. bit 3 ~1: cps 2 - cps0 , pca counter clock sou rce select bits. cps2 cps1 cps0 pca clock source 0 0 0 internal clock, (system clock) /12 0 0 1 internal clock, (system clock) / 2 0 1 0 timer 0 overflow 0 1 1 external clock at the eci pin
megawin mg82fg5b xx data sheet 143 1 0 0 reserved 1 0 1 sysclk 1 1 0 s1brg overflow 1 1 1 reserv ed bit 0: ecf , enable pca counter overflow interrupt. 0: disables an interrupt when cf bit (in ccon register) is set. 1 : e nables an interrupt when cf bit (in ccon register) is set. the ccon register shown below contains the run control bit for the pca a nd the flags for the pca timer and each module. to run the pca the cr bit (ccon.6) must be set by software. the pca is shut off by clearing this bit. the cf bit (ccon.7) is set when the pca counter overflows and an interrupt will be generated if the ecf bi t in the cmod register is set. the cf bit can only be cleared by software. ccf0 to ccf5 are the interrupt flags for module 0 to module 5, respectively, and they are set by hardware when either a match or a capture occurs. these flags also can only be clear ed by software. the pca interrupt system is shown figure 19? 3 . ccon: pca counter control register sfr page = 0~f sfr address = 0xd8 reset = 0000 - 0000 7 6 5 4 3 2 1 0 cf cr ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 r/w r /w r /w r /w r /w r/w r/w r/w bit 7: cf , pca counter overflow flag. 0: only be cleared by software. 1: set by hardware when the counter rolls over. cf flag can generate an interrupt if bit ecf in cmod is set. cf may be set by either hardware or software . b it 6: cr , pca counter run control bit. 0: must be cleared by software to turn the pca counter off. 1: set by software to turn the pca counter on. bit 5: ccf5 , pca module 5 interrupt flag. 0: must be cleared by software. 1: set by hardware when a match or capture occurs. bit 4: ccf 4, pca module 4 interrupt flag. 0: must be cleared by software. 1: set by hardware when a match or capture occurs. bit 3: ccf 3, pca module 3 interrupt flag. 0: must be cleared by software. 1: set by hardware when a match or capt ure occurs. bit 2: ccf 2, pca module 2 interrupt flag. 0: must be cleared by software. 1: set by hardware when a match or capture occurs. bit 1: ccf 1, pca module 1 interrupt flag. 0: must be cleared by software. 1: set by hardware when a match or capture occurs. bit 0: ccf 0, pca module 0 interrupt flag. 0: must be cleared by software. 1: set by hardware when a match or capture occurs.
144 mg82fg5b xx data sheet megawin figure 19? 3 . pca interrupt system ccf 0 ccf 1 ccf 2 ccf 3 ccf 4 ccf 5 cr cf ccon eie 1 . epca cmod . ecf ccapmn . 0 ( n = 0 ~ 5 ) module 5 module 4 module 3 module 2 module 1 module 0 ie . ea to interrupt priority processing pca timer / counter eccf 0 ~ eccf 5 19.3. compare/capture modules each o f the compare/capture module 0~5 has a mode register called ccapmn (n = 0,1,2,3, 4 or 5 ) to select which function it will perform. note the eccfn bit which enables an interrupt to occur when a module's interrupt flag is set. ccapmn: pca module compare/capt ure register, n=0~5 sfr page = 0 only sfr address = 0xda~0xdf reset = 0 000- 0000 7 6 5 4 3 2 1 0 dten ecomn cappn capnn matn togn pwmn eccfn r/ w r/w r /w r /w r /w r/w r/w r/w bit 7: detn, reserved for test mode . software must write ? 0 ? on this bit when the ccapmn is written. bit 6: ecomn , enable comparator 0: disable the digital comparator function. 1: e nables the digital comparator function. bit 5: cappn , capture positive enabled . 0: disable the pca capture function on cexn positive edge detected. 1: e nable the pca capture function on cexn positive edge detected. bit 4: ca pnn , capture negative enabled . 0: disable the pca capture function on cexn positive edge detected. 1: e nable the pca capture function on cexn negative edge detected . bit 3: matn , ma tch control. 0: disable the digital comparator match event to set ccfn.
megawin mg82fg5b xx data sheet 145 1: a match of the pca counter with this module?s compare/capture r egister causes the ccfn bit in ccon to be set. bit 2: togn , toggle control. 0: disable the digital comparator match e vent to toggle cexn. 1: a match of the pca counter with this module?s compare/capture register causes the cexn pin to toggle. bit 1: pwmn , pwm control. 0: disable the pwm mode in pca module. 1: e nable the pwm function and cause cexn pin to be used as a pu lse width modulated output. bit 0: eccfn , enable ccfn interrupt. 0: disable compare/capture flag ccfn in the ccon register to generate an interrupt. 1: enable compare/capture flag ccfn in the ccon register to generate an interrupt. note: the bits capnn ( ccapmn.4) and cappn (ccapmn.5) determine the edge on which a capture input will be active. if both bits are set, both edges will be enabled and a capture will occur for either transition. module 6~7 only has the pwm function which is enabled by setting c capmn. pwmn (n = 6 or 7). there is no interrupt flag in these two modules. ccapmn: pca module compare/capture register, n=6~7 sfr page = 1 only sfr address = 0xda~0xdb reset = 0xxx - xx0x 7 6 5 4 3 2 1 0 bme6 -- -- -- -- -- pwmn -- r/w w w w w w r/w w bit 7~2: reserved. software must write ? 0 ? on these bits when ccapm6 or ccapm7 is written. bit 1: pwmn , pwm control. 0: disable the pwm mode in pca module. 1: e nable the pwm function and cause pwm6 or pwm7 pin to be used as a pulse width modulated output. bit 0: reserved. software must write ? 0 ? on this bit when ccapm6 or ccapm7 is written. each module also has a pair of 8 - bit compare/capture registers (ccapnh, ccapnl) associated with it. these registers are used to store the time when a capture event o ccurred or when a compare event should occur. when a module is used in the pwm mode, in addition to the above two registers, an extended register pcapwmn is used to improve the range of the duty cycle of the output. the improved range of the duty cycle sta rts from 0%, up to 100%, with a step of 1/256. ccapnh: pca module n capture high register, n=0~ 5 sfr page = 0 only sfr address = 0xfa~0xff reset = 0000 - 0000 7 6 5 4 3 2 1 0 ccapnh.7 ccapnh. 6 ccapnh.5 ccapnh.4 ccapnh.3 ccapnh.2 ccapnh.1 ccapnh.0 r/w r/ w r/w r/w r/w r/w r/w r/w ccapnh: pca module n captur e high register, n=6~7 sfr page = 1 only sfr address = 0xfa~0xfb reset = 0000 - 0000 7 6 5 4 3 2 1 0 ccapnh.7 ccapnh. 6 ccapnh.5 ccapnh.4 ccapnh.3 ccapnh.2 ccapnh.1 ccapnh.0 r/w r/w r/w r/w r/w r/w r/ w r/w
146 mg82fg5b xx data sheet megawin ccapn l : pca module n capture low register, n=0~ 5 sfr page = 0 only sfr address = 0xea~0xef reset = 0000 - 0000 7 6 5 4 3 2 1 0 ccapn l .7 ccapn l . 6 ccapnl.5 ccapnl.4 ccapnl.3 ccapnl.2 ccapnl.1 ccapnl.0 r/w r/w r/w r/w r/w r/w r/w r/w ccapn l : pca module n capture low register, n= 6~7 sfr page = 1 only sfr address = 0xea~0xeb reset = 0000 - 0000 7 6 5 4 3 2 1 0 ccapn l .7 ccapn l . 6 ccapnl.5 ccapnl.4 ccapnl.3 ccapnl.2 ccapnl.1 ccapnl.0 r/w r/w r/w r/w r/w r/w r/w r/w pcapwmn: pwm mode auxiliary register, n=0~5 sfr page = 0 only sfr address = 0xf2~0xf7 reset = 0000 - 0000 7 6 5 4 3 2 1 0 pnrs1 pnrs0 pnps2 pnps1 pnps0 pninv ecapnh ecapnl r/w r/w r /w r /w r /w r/w r/w r/w bit 1: ecapnh , extended 9th bit (msb bit), associated with ccapnh to become a 9- bit register used in pwm mode. bit 0: ecapnl , extended 9th bit (msb bit), associated with ccapnl to become a 9 - bit register used in pwm mode. pcapwmn: pwm mode auxiliary register, n= 6 ~ 7 sfr page = 1 onl y sfr address = 0xf2~0xf3 reset = 0000 - 0000 7 6 5 4 3 2 1 0 pnrs1 pnrs0 pnps2 pnps1 pnps0 pninv ecapnh ecapnl r/w r/w r /w r /w r /w r/w r/w r/w bit 1: ecapnh , extended 9th bit (msb bit), associated with ccapnh to become a 9 - bit register used in pwm mode. bit 0: ecapnl , extended 9th bit (msb bit), a ssociated with ccapnl to become a 9 - bit register used in pwm mode.
megawin mg82fg5b xx data sheet 147 19.4. operation modes of the pca table 19 ? 1 shows the ccapmn register settings for the various pca functions. table 19 ? 1 . pca module modes ecomn cappn capnn matn togn pwmn eccfn module function 0 0 0 0 0 0 0 no operation x 1 0 0 0 0 x 16- bit capture by a positive - edge trigger on cexn x 0 1 0 0 0 x 16- bit capture by a negative - edge trigger on cexn x 1 1 0 0 0 x 16- bit capture by a transition on cexn 1 0 0 1 0 0 x 16- bit software timer 1 0 0 1 1 0 x 16- bit high speed output 1 0 0 0 0 1 0 pulse width modulator (pwm) 19.4.1. capture mode to use one of the pca modules in the capture mode, either one or both o f the bits capn and capp for that module must be set. the external cex input for the module is sampled for a transition. when a valid transition occurs the pca hardware loads the value of the pca counter registers (ch and cl) into the module?s capture regi sters (ccapnl and ccapnh). if the ccfn and the eccfn bits for the module are both set, an interrupt will be generated. figure 19? 4 . pca capture mode ccf 0 ccf 1 ccf2 ccf3 ccf4 ccf5 cr cf ccon eccfn pwmn togn matn capnn cappn ecomn dten ccapmn n= 0 to 5 ccapnl ccapnh ch cl capture cexn (to ccfn) pca timer/counter pca interrupt 0 0 0 0 1 1 cappn or capnn =1 clrl chrl overflow reload 0/1 0
148 mg82fg5b xx data sheet megawin 19.4.2. 16- bit software timer mode the pca modules can be used as software timers by setting both the ecom and mat bits in the module?s ccapmn register. the pca timer will be compared to the module?s capture registers, and when a match occurs an interrupt will occur if the ccfn and the eccfn bits for the module are both set. figure 19? 5 . pca software timer mode ccf 0 ccf 1 ccf2 ccf3 ccf4 ccf5 cr cf ccon eccfn pwmn togn matn capnn cappn ecomn dten ccapmn, n= 0 to 5 ccapnl ccapnh ch cl enable (to ccfn) pca timer/counter pca interrupt 0 0 1 0 0 16-bit comparator 1 0 write to ccapnl reset write to ccapnh match clrl chrl overflow reload 0/1 0
megawin mg82fg5b xx data sheet 149 19.4.3. high speed output mode in this mode the cex output associated with the pca module will toggle each time a match occurs between the pca counter and the module?s capture registers. to activate this mode, the tog, mat and ecom bits in the module?s ccapmn register must be set. figure 19? 6 . pca high speed output mode ccf 0 ccf 1 ccf2 ccf3 ccf4 ccf5 cr cf ccon eccfn pwmn togn matn capnn cappn ecomn dten ccapmn, n= 0 to 5 ccapnl ccapnh ch cl enable (to ccfn) pca timer/counter pca interrupt 0 1 1 0 0 16-bit comparator 1 0 write to ccapnl reset write to ccapnh match toggle cexn clrl chrl overflow reload 0/1 0
150 mg82fg5b xx data sheet megawin 19.4.4. pwm mode all of the pca modules can be used as pwm outputs. the frequency of the output depends on the clock source for the pca timer. all of the modules will have the same frequency of output because they all share the pca timer. the duty cycle of each module is determined by the mod ule?s capture register ccapnl and the extended 9 th bit, ecapnl. when the 9 - bit value of { 0, [cl] } is less than the 9 - bit value of { ecapnl, [ccapnl] } the output will be low, and if equal to or greater than the output will be high. when cl overflows fro m 0xff to 0x00, { ecapnl, [ccapnl] } is reloaded with the value of { ecapnh, [ccapnh] }. this allows updating the pwm without glitches. the pwmn and ecomn bits in the module?s ccapmn register must be set to enable the pwm mode. using the 9 - bit comparison, the duty cycle of the output can be improved to really start from 0%, and up to 100%. the formula for the duty cycle is: duty cycle = 1 ? { ecapnh, [ccapnh] } / 256 . where, [ccapnh] is the 8 - bit value of the ccapnh register, and ecapnh (bit - 1 in the pca pwmn register) is 1 - bit value. so, { ecapnh, [ccapnh] } forms a 9 - bit value for the 9 - bit comparator. for examples, a. if ecapnh=0 & ccapnh=0x00 (i.e., 0x000), the duty cycle is 100%. b. if ecapnh=0 & ccapnh=0x40 (i.e., 0x040) the duty cycle is 75%. c. if ecapnh=0 & ccapnh=0xc0 (i.e., 0x0c0), the duty cycle is 25%. d. if ecapnh=1 & ccapnh=0x00 (i.e., 0x100), the duty cycle is 0%. figure 19? 7 . pca pwm mode eccfn pwmn togn matn capnn cappn ecomn dten ccapmn n = 0 to 7 ccapnl ccapnh cl enable pca timer / counter 0 / 1 1 1 0 0 9 - bit comparator ecapnh ecapnl ( fixed 0 ) 0 / 1 0 cl overflow 9 bits 9 bits 9 bits s r q q ccf 0 ccf 1 ccf 2 ccf 3 ccf 4 ccf 5 cr cf ccon ( to ccfn ) match matn 9 th bit pwm 7 ~ 0 output 0 1 pninv pwmnh pwmnl 0 1 q port i / o pwmn clrl reload 0 0 pca interrupt eccfn
megawin mg82fg5b xx data sheet 151 19.4.5. enhance pwm mode the pca provides the va riable pwm mode to enhance the control capability on pwm application . there are additional 10/12/16 bits pwm can be assigned in each channel and each pwm channel with different resolution and different phase delay can operate concurrently. figure 19? 8 . pca enhance pwm for 10/12/16 - bit pwm mode eccfn pwmn togn matn capnn cappn ecomn dten ccapmn, n= 0 to 7 enable 0/1 1 1 0 0 0/1 0 overflow pwm7~0 output s r q q 0 1 pninv ccf0 ccf1 ccf2 ccf3 ccf4 ccf5 cr cf ccon (to ccfn) match matn ccapnl ccapnh ch cl pca timer/counter 11/13/17-bit comparator 11/13/17th bit 17 bits clrl chrl reload pwmnh pwmnl 0 1 q port i/o pwmn ecapnl 1b '0' ecapnh reload 11/13/17th bit 0 pca interrupt eccfn figure 19? 9 . pca enhance pwm for buffer mode (pwm6/7 have no dead - time control function) eccfn pwmn togn matn capnn cappn ecomn dten ccapmn, n= 0 to 7 enable 0/1 1 1 0 0 0/1 0 overflow pwm0, pwm2, pwm4, pwm6 output s r q q pninv, n= 0, 2, 4, 6 ccf0 ccf1 ccf2 ccf3 ccf4 ccf5 cr cf ccon (to ccfn) match matn ccapnl ccapnh ch cl pca timer/counter 11/13/17-bit comparator 11/13/17 bits 17 bits clrl chrl reload pwmnh pwmnl 0 1 q port i/o pwmn, n= 0, 2, 4, 6 ecapnl 1b '0' ecapnl ccapnl ccapnh n= 1, 3, 5, 7 n= 0, 2, 4, 6 reload 11/13/17th bit 11/13/17th bit dead time control dpwmnh dpwmnl 0 1 0 1 pninv, n= 1, 3, 5, 7 pwm1, pwm3, pwm5, pwm7 output 0 1 port i/o pwmn, n= 1, 3, 5, 7 0/1 enabled by: dte0, det2 or det4 pca interrupt eccfn pwm6/7-pair has no dead-time control function
152 mg82fg5b xx data sheet megawin paoe: pwm additi onal output enable register sfr page = 0~f sfr address = 0xf1 reset = 0001 - 1001 7 6 5 4 3 2 1 0 p47op4 p41op2 p40op2 p24op2 p26op4 p21op0 p20op0 p22op0 r/w r/w r/w r/w r/w r/w r/w r/w bit 7: p47op4, p47 output p wm4. 0: disable p47 to output pwm4. default is disabled . 1: enable p47 to output pwm4. bit 6: p41op2, p41 output pwm2. 0: disable p41 to output pwm2. default is disabled . 1: enable p41 to output pwm2. bit 5: p40op2, p40 output pwm2. 0: disable p40 to o utput pwm2. default is disabled . 1: enable p40 to output pwm2. bit 4: p24op2, p24 output pwm2. 0: disable p24 to output pwm2. 1: enable p24 to output pwm2. default is enabled . bit 3: p26op4, p26 output pwm4. 0: disable p26 to output pwm4. 1: enable p26 to output pwm4. default is enabled . bit 2: p21op0, p21 output pwm0. 0: disable p21 to output pwm0. default is disabled . 1: enable p21 to output pwm0. bit 1: p20op 0 , p20 output pwm0. 0: disable p20 to output pwm0. default is disabled . 1: enable p20 to output pwm0. bit 0: p22op0, p22 output pwm0. 0: disable p22 to output pwm0. 1: enable p22 to output pwm0. default is enabled .
megawin mg82fg5b xx data sheet 153 pcapwmn: pwm mode auxiliary register, n=0~ 7 sfr page = 0 if n = 0~1 sfr page = 1 if n = 6~7 sfr page = 0~f if n = 2~5 sfr address = 0xf2~0xf7 reset = 0000 - 0000 7 6 5 4 3 2 1 0 pnrs1 pnrs0 pnps2 pnps1 pnps0 pninv ecapnh ecapnl r/w r/w r /w r /w r /w r/w r/w r/w bit 7~6: pwmn resolution setting 1~0. 00: 8 bit pwmn, the overflow is active when [ch, cl] counts xxxx - xxxx - 1111- 1 111 ? xxxx - xxxx - 0000- 0000. 01: 10 bit pwmn, the overflow is active when [ch, cl] counts xxxx - xx11 - 1111- 1111 ? xxxx- xx00 - 0000- 0000. 10: 12 bit pwmn, the overflow is active when [ch, cl] counts xxxx - 1111- 1111- 111 ? xxxx- 0000- 0000- 0000. 11: 16 bit pwmn, the o verflow is active when [ch, cl] counts 1111 - 1111 - 1111 - 1111 ? 0000 - 0000 - 0000 - 0000. bit 5~3: pwmn phase setting 2~0. 000: the enabled pwm channel starts at 0 degree. 001: the enabled pwm channel starts at 90 degree. 010: the enabled pwm channel starts at 180 degree. 011: the enabled pwm channel starts at 270 degree. 100: the enabled pwm channel starts at 120 degree. 101: the enabled pwm channel starts at 240 degree. 110: the enabled pwm channel starts at 60 degree. 111: the enabled pwm channel starts at 300 d egree. in default pca pwm mode, all pwm outputs are cleared on cl overflow. all pwm outputs go to low simultaneously and are set to high by the match event from individual ccapnl setting and cl counter. this mode pwm behaves a same phase pwm because the p wm outputs always start at the same time. the pca enhanced pwm mode provides the phase delay function on each pwm channel with different pwm resolution. the following table i ndicates the counter value to clear pwm output if comparator result is matched. th e set condition of pwm outputs keeps the original matched event by {ccfnh, ccfnl} and {ch, cl}. so after setting the phase delay parameter , software only take care the value of the pwm end count (pwm output set) to implement the variable phase delay pwm. phase 0 ? /360 ? 90? 180? 270? 120? 240? 60 ? ?
154 mg82fg5b xx data sheet megawin cmod: pca counter mode register sfr page = 0~f sfr address = 0xd9 reset = 00 00- 0 000 7 6 5 4 3 2 1 0 cidl bme4 bme2 bme0 cps2 cps1 cps0 ecf r/w r/w r/w r/w r/w r/w r/w r/w bit 6: bme4, buffer mode enable on pca module 4/5. it is only valid on both of pca module 4 and module 5 in capture mode or pwm mode. 0: pca module 4/5 buffe r mode disabled. 1: pca module 4/5 buffer mode enabled. bit 5: bme2, buffer mode enable on pca module 2/3. it is only valid on both of pca module 2 and module 3 in capture mode or pwm mode. 0: pca module 2/3 buffer mode disabled. 1: pca module 2/3 buffer mode enabled. bit 4: bme0, buffer mode enable on pca module 0/1. it is only valid on both of pca module 0 and module 1 in capture mode or pwm mode. 0: pca module 0/1 buffer mode disabled. 1: pca module 0/1 buffer mode enabled. pwmcr: pwm control registe r sfr page = 0~f sfr address = 0xbc reset = 00x0 - 0000 7 6 5 4 3 2 1 0 pcae exdt -- p bk f p bk m p bk s2 p bk s1 p bk s0 r/ w r/w w r/w r/w r/w r/w r/w bit 7: pcae, pwm central aligned enabled. pcae controls the enabled pwm channels to central aligned modulati on including buffer mode pwm or non - buffer mode pwm. in this pwm mode, the pwm frequency is the half of edge aligned mode. this function is only active on pwmo0~5. 0: set the pwm function with edge aligned modulation. 1: enable the pwm function with centra l aligned modulation. figure 19? 10 . waveform of edge aligned pwm and central aligned pwm pwm duty cycle 0 pwm period 65536 C {chrl,clrl} pwmnh 65536 - {ccapnh,ccapnl} edge aligned pwm (16-bit) duty cycle = duty cycle = 0 pwm period (65536 C{chrl,clrl}) x 2 pwmnh (65536 - {ccapnh,ccapnl}) central aligned pwm (16-bit) pwm duty cycle bit 6: exdt: extend dead - time in pwm period. this enabled function will corrupt the non - pwm channel functio n. such as capture mode, software timer mode and high speed output mode. the waveform of exdt control bit is show in figure 1 - 7. 0: disable m + 2p . 1: enable m + 2p on enabled pwm channel.
megawin mg82fg5b xx data sheet 155 bit 5: reserved. software must write ? 0 ? on this bit when the pw mcr is written. bit 4: pb k f, pwm b r eak event flag. this bit is set by pb k s2~0 controlled and software programming. if this flag is set, the enabled pwm channel 0~5 will be blocked and the output pins keep the original gpio state. 0: there is no pwm break event happened. it is only cleared by software. 1: there is a pwm break event happened or software triggers a pwm break. bit 3: pb k m, pwm break mode selection. 0: latched mode. 1: cycle - by - cycle mode. figure 19? 11. latch mode waveform of pwm break control pwmon by break control break event input pwmnh ( non-break) pwm period: m m pbkf software clear m latched mode of pwm break control cexn switched to port i/o cexn switched to port i/o figure 19? 12. cycle - by - cycle mode waveform of pwm break control pwmon by break control break event input pwmnh ( non - break ) pwm period : m m pbkf software clear m software clear cycle - by - cycle mode of pwm break control cexn switched to port i / o cexn switched to port i / o
156 mg82fg5b xx data sheet megawin bit 2~0: pbks2~0, pwm break source selection. the pwm b reak function is only ac tive on pwmo0~5. pfcs[2:0] pwm break event source 000 disable 001 nint0 active 010 nint1 active 011 nint0 active & nint1 active 100 nint2 active 101 nint0 active & nint2 active 110 nint1 active & nint2 active 111 nint0 active & nint1 active & nint2 active figure 19? 13. pwm break source pbks 0 pbks1 pbks2 pwm break control h: true pbkf set nint0 input 0 1 int0h (auxr0.0) 0 1 3 clock filter x0flt (xicfg.0) nint1 input 0 1 int1h (auxr0.1) 0 1 3 clock filter x1flt (xicfg.1) nint2 input 0 1 int2h (xicon.3) 0 1 3 clock filter x2flt (xicfg.2)
megawin mg82fg5b xx data sheet 157 pdtcr: pwm dead - time control register sfr page = 0~f sfr address = 0xbd r eset = 0000 - 0000 7 6 5 4 3 2 1 0 dtps1 dtps0 dt5 dt4 dt3 dt2 dt1 dt0 r/w r/w r/w r/w r/w r/w r/w r/w bit 7~6: dtps1~0, clock pre - scaler of dead - time counter. dtps[1:0] pre - scaler selection 00 sysclk 01 sysclk/2 10 sysclk/4 11 sysclk/8 bit 5~0: dt5~0, dead - time period control bits. dt[5:0] dead - time period 00000 dead - time disa bled 00001 pre - scaler clock x 1 00010 pre - scaler clock x 2 00011 pre - scaler clock x 3 ? .. ?? 11110 pre - scaler clock x 30 11111 pre - scaler clock x 31 ccapmn: pca module compare/capture register, n=0~5 sfr page = 0 only sfr address = 0xda~0xdf res et = 0000 - 0000 7 6 5 4 3 2 1 0 dten ecomn cappn capnn matn togn pwmn eccfn r/w r/w r /w r /w r /w r/w r/w r/w bit 7: dten. enable dead - time control on pwmhn/pwmln complemented output pair. this bit is only valid on n= 0, 2 and 4 and the dead - time function is active when pwm channel is operating in buffer mode. t he channel buffer mode is enabled by bme0, bme2 or bme4 in cmod. 0: disable the dead - time control on pwmn /pwmn+1 output. (n= 0, 2, 4) 1: enable the dead - time control on pwmn /pwmn+1 output. (n= 0, 2, 4)
158 mg82fg5b xx data sheet megawin figure 19? 14. waveform of pwm dead - time control pwmnh dpwmnh dpwmnl pwmnl pwm period : m n m p p m : 65536 - {chrl,clrl} n: 65536 - {ccapnh,ccapnl} p: 2 (dtps1, dtps0) x (dt[5 :0]) m - n n - p m - n - p dpwmnh w/ dead-time control dpwmnl w/ dead-time control p p m - n n pwm period : m + px2 dpwmnh w/ dead-time control dpwmnl w/ dead-time control p p n x 2 pwm period : mx2 + px 2 normal 16-bit pwm pwm with dead-time control pwm with dead-time control & exdt enabled & edge aligned pwm with dead-time control & exdt enabled & central aligned m - n n p
megawin mg82fg5b xx data sheet 159 19.5. pca sample code (1). required function: set pwm2/pwm3 output with 25% & 75% duty cycle assembly code example: pwm2_pwm3: mov ccon,#00h ; stop cr mov cmod,#02h ; pca clock source = system clock / 2 mov ch,#00h ; initial state mov cl,#00h mov chrl,#00h ; initial reload mov clrl,#00h ; mov c ca pm2,# ( ecom2 + pwm2) ; ena ble pca module 2 (pwm mode) mov ccap2h,#0c0h ; 25% mov ccap2l,#0c0h mov ccapm3,#( ecom3 + pwm3) ; enable pca module 3 (pwm mode) mov ccap3h,#40h ; 75% mov ccap3l,#40h ; mov p2m0,#00010001b ; enable p2.0 & p2.4 pull - u p setb cr ; start pca c code example: void main(void) { // set pca ccon = 0x00; // disable pca & clear ccf0, ccf1, cf flag cmod = 0x02; // pca clock source = system clock / 2 cl = 0x00; ch = 0x00; chrl = 0x00; clrl = 0x00; // pca counter range // ---------------------------------------------- ccapm2 = ecom2 + pwm2 ; // module 2 (non - inverted) ccap2h = 0xc0; ccap2l = 0xc0; // 25% ccapm3 = ecom3 + pwm3 ; // module 3 ccap3h = 0x40; ccap3l = 0x40; // 75 % // ---------------------------------------------- p2m0 = 0x11; cr = 1; // start pca's pwm output while (1); }
160 mg82fg5b xx data sheet megawin 20. serial peripheral inter face (spi) the mg82fg5bxx provides a high - speed serial communication interface, the spi interface. spi is a full - duplex, high - speed and synchronous communication bus with two operation modes: master mode and slave mode. up to 12mhz can be supported in mas ter mode under a 48mhz system clock. it has a transfer completion flag (spif) , write collision flag (wcol) and mode fault flag (modf), in the spi status register (spstat). a nd a specially designed transmit holding register (thr) improves the transmit perf ormance compared to the conventional spi and thrf flag indicates the thr is full or empty . spibsy read - only flag reports the busy state in spi engine. figure 20? 1 . spi block diagram / 4 / 8 /16 /32 /64 /128 output shift register (osr) input shift register (isr) spi control i/o control ssig spen dord mstr cpol cpha spr1 spr0 spif wcol thrf spibsy modf -- -- spr2 spcon spstat sysclk spiclk (p1.7/ p4.0) miso (p1. 6/p 4.1 ) mosi (p1. 5/p2 .1) nss (p1.4 /p2. 0) s1tof/ 6 s1tof t0of/6 t0of transmit holding register (thr) receive holding register (rhr) cpu write spdat set thrf if thrf=0, or set wcol if thrf=1 clear thrf cpu read spdat auto-load auto-load the spi interface h as four pins: miso (p1.6), mosi (p1.5), spiclk (p1.7) and n ss (p1.4): ? spiclk, mosi and miso are typically tied together between two or more spi devices. data flows from master to slave on the mosi pin (master out / slave in) and flows from slave to mast er on the miso pin (master in / slave out). the spiclk signal is output in the master mode and is input in the slave mode. if the spi system is disabled, i.e., spen (spctl.6) = 0, these pins function as normal i/o pins. ? /ss is the optional slave select pin. in a typical configuration, an spi master asserts one of its port pins to select one spi device as the current slave. an spi slave device uses its n ss pin to determine whether it is selected. the /ss is ignored if any of the following conditions are t rue: - if the spi system is disabled, i.e. spen (spctl.6) = 0 (reset value). - if the spi is configured as a master, i.e., mstr (spctl.4) = 1, and p1.4 ( n ss) is configured as an output. - if the /ss pin is ignored, i.e. ssig (spctl.7) bit = 1, this pin is configured for port functions. note: see the auxr1 in section ? 5.3 alternate function redirection ? , for its alternate pin - out option. note that even if the spi is con figured as a master (mstr=1), it can still be converted to a slave by driving the /ss pin low (if ssig=0). should this happen, the spif bit (spstat.7) will be set. (see section ? 20.2.3 mode change on nss - pin ? )
megawin mg82fg5b xx data sheet 161 20.1. typical spi configurations 20.1.1. single master & single slave for the master: any port pin, including p1.4 ( n ss), can be used to drive the n ss pin of the slave. for the slave: ssig is ?0?, and n ss pin is used to deter mine whether it is selected. figure 20? 2 . spi single master & single slave configuration master slave miso mosi spiclk port pin miso mosi spiclk nss 20.1.2. dual device, where either can be a master or a slave two devices are connected to each other and either device can be a master or a slave. when no spi operation is occurring, both can be configured as masters with mstr=1, ssig=0 and p1.4 (n ss) configured in quasi - bidirectional mode. when any device initiates a transfer, it can configure p1.4 as an output and drive it low to force a ?mode change to slave? in the other device. (see section ? 20.2.3 mode change on nss - pin ? ) figure 20? 3 . spi dual device configuration, where either can be a master or a slave master / slave slave/ master miso mosi spiclk nss miso mosi spiclk nss 20.1.3. single master & multiple slaves for the master: any port pin, including p1.4 ( n ss), can be used to drive the n ss pins of the slaves. for all the slaves: ssig is ?0?, and n ss p in are used to determine whether it is selected. figure 20? 4 . spi single master multiple slaves configuration master slave # 1 miso mosi spiclk port pin 1 miso mosi spiclk nss slave # 2 miso port pin 2 nss spiclk mosi
162 mg82fg5b xx data sheet megawin 20.2. configuring the spi table 20 ? 1 shows configura tion for the master/slave modes as well as usages and directions for the modes. table 20 ? 1 . spi master and slave selection spen (spctl.6) ssig (spctl.7) /ss - pin mstr (spctl.4) mode miso - pin mosi - pin spiclk - pin remarks 0 x x x spi disabled input input input p1.4~p1.7 are used as general port pins. 1 0 0 0 salve (selected) output input input selected as slave. 1 0 1 0 slave (not selected) hi - z input input not selected. 1 0 0 1 ? 0 slave (by mode change) output input input mode change to slave if n ss pin is driven low, and mstr will be cleared to ? 0 ? by h/w automatically. 1 0 1 1 master (idle) input hi - z hi - z mosi and spiclk are at high impedance to avoid bus contention when the master is idle. maste r (active) output output mosi and spiclk are push - pull when the master is active. 1 1 x 0 slave output input input 1 1 x 1 master input output output ? x ? means ?don? t care ? . 20.2.1. additional considerations for a slave when cpha is 0, ssig must be 0 and n ss pin must be negated and reasserted between each successive serial byte transfer. note the spdat register cannot be written while n ss pin is active (low), and the operation is undefined if cpha is 0 and ssig is 1. when cpha is 1, ssig may be 0 or 1. if ssig=0, the n ss pin may remain active low between successive transfers (can be tied low at all times). this format is sometimes preferred for use in systems having a single fixed master and a single slave configuration. 20.2.2. additional considerations for a m aster in spi, transfers are always initiated by the master. if the spi is enabled (spen=1) and selected as master, writing to the spi data register (spdat) by the master starts the spi clock generator and data transfer. the data will start to appear on mo si about one half spi bit - time to one spi bit - time after data is written to spdat. before starting the transfer, the master may select a slave by driving the n ss pin of the corresponding device low. data written to the spdat register of the master is shi fted out of mosi pin of the master to the mosi pin of the slave. and, at the same time the data in spdat register of the selected slave is shifted out on miso pin to the miso pin of the master. after shifting one byte, the spi clock generator stops, setti ng the transfer completion flag (spif) and an interrupt will be created if the spi interrupt is enabled. the two shift registers in the master cpu and slave cpu can be considered as one distributed 16 - bit circular shift register. when data is shifted from the master to the slave, data is also shifted in the opposite direction simultaneously. this means that during one shift cycle, data in the master and the slave are interchanged.
megawin mg82fg5b xx data sheet 163 20.2.3. mode change on nss - pin if spen=1, ssig=0, mstr=1 and /ss pin=1, the spi is enabled in master mode. in this case, another master can drive this pin low to select this device as an spi slave and start sending data to it. to avoid bus contention, the spi becomes a slave. as a result of the spi becoming a slave, the mosi and spiclk pins are forced to be an input and miso becomes an output. the spif flag in spstat is set, and if the spi interrupt is enabled, an spi interrupt will occur. user software should always check the mstr bit. if this bit is cleared by a slave select and the us er wants to continue to use the spi as a master, the user must set the mstr bit again, otherwise it will stay in slave mode. 20.2.4. transmit holding register full flag to speed up the spi transmit performance, a specially designed transmit holding register (th r) improves the latency time between byte to byte transmit ting in cpu data moving. and a set thr - full flag, thrf (spstat.5) , indicates the data in thr is valid and waiting for transmitting. if thr is empty (thrf=0), software writes one byte data to spdat w ill store the data in thr and set the thrf flag. if output shift register (osr) is empty, hardware will move thr data into osr immediately and clear the thrf flag. in spi mater mode, valid data in osr triggers a spi transmit. in spi slave mode, valid data in osr is waiting for another spi master to shift out the data. if thr is full (thrf=1), software writes one byte data to spdat will set a write collision flag, wcol (spstat.6). 20.2.5. write collision the spi in mg82fg5bxx is double buffered data both in the t ransmit direction and in the receive direction. new data for transmission cannot be written to the thr until the thr is empty . the read - only flag, thrf, indicates the thr is full or empty . the wcol (spstat.6) bit is set to indicate data collision when the data register is written during set thrf . in this case, the spdat writing operation is ignored. while write collision is detected for a master or a slave, it is uncommon for a master because the master has full control of the transfer in progress. the sla ve, however, has no control over when the master will initiate a transfer and therefore collision can occur. wcol can be cleared in software by writing ?1? to the bit. 20.2.6. spi clock rate select the spi clock rate selection (in master mode) uses the spr1 and spr0 bits in the spc on register and spr2 in the spstat register , as shown in table 20 ? 2 . table 20 ? 2 . spi serial clock rates spr 2 spr1 spr0 spi clock selection spi clock rate @ sysclk = 12mhz spi clock rate @ sysclk = 48 mhz 0 0 0 sysclk/ 4 3 mhz 12 mhz 0 0 1 sysclk/8 1.5 mhz 6 mhz 0 1 0 sysclk/16 750 khz 3 m hz 0 1 1 sysclk/32 375 khz 1.5 mhz 1 0 0 sysclk/64 187.5 khz 750 khz 1 0 1 sysclk/128 93.75 khz 375 khz 1 1 0 s1tof/6 variable variable 1 1 1 t0of/6 variable variable note: 1. sysclk is the system clock . 2. s1tof is uart1 baud - rate generator overflow. 3. t 0 of is timer 0 overflow.
164 mg82fg5b xx data sheet megawin 20.3. data mode clock phase bit (cpha) allows the user to set the edges for sampling and chan ging data. the clock polarity bit, cpol, allows the user to set the clock polarity. the following figures show the different settings of clock phase bit, cpha. figure 20? 5 . s pi slave transfer format with cph a=0 spiclk (cpol=0) spiclk (cpol=1) clock cycle 1 2 3 4 5 6 7 8 mosi miso dord=0 dord=1 msb lsb 6 1 5 2 4 3 3 4 2 5 1 6 msb lsb 1st bit out slave intput slave output 1st bit in data sampled nss (if ssig=0) not defined this edge is used by the slave to shift out the 1st bit of each data byte while cpha=0 figure 20? 6 . slave transfer format with cph a=1 slave w/ cpha=1 spiclk ( cpol=0) spiclk (cpol=1) clock cycle 1 2 3 4 5 6 7 8 mosi miso dord=0 dord=1 msb lsb 6 1 5 2 4 3 3 4 2 5 1 6 msb lsb 1st bit out 1st bit in data sampled nss (if ssig=0) slave intput slave output not defined
megawin mg82fg5b xx data sheet 165 figure 20? 7 . s pi master transfer format with cpha=0 spiclk (cpol=0) spiclk (cpol=1) clock cycle 1 2 3 4 5 6 7 8 mosi miso dord=0 dord=1 msb lsb 6 1 5 2 4 3 3 4 2 5 1 6 msb lsb enable spi 1st bit out master output master input 1st bit in data sampled nss (if ssig=0) figure 20? 8 . s pi master transfer format with cpha= 1 spiclk (cpol=0) spiclk (cpol=1) clock cycle 1 2 3 4 5 6 7 8 mosi miso dord=0 dord=1 msb lsb 6 1 5 2 4 3 3 4 2 5 1 6 msb lsb 1st bit out master output master input 1st bit in data sampled nss (if ssig=0)
166 mg82fg5b xx data sheet megawin 20.4. spi register the following special function registers are related to the spi operation: spcon: spi control register sfr page = 0~f sfr address = 0x85 reset= 0000 - 0100 7 6 5 4 3 2 1 0 ssig spen dord mstr cpol cpha spr1 spr0 r /w r /w r /w r/w r /w r /w r/w r/w bit 7: ssig , n ss is ignored . 0: t he n ss pin decides whether the device is a master or slave. 1: mstr decides whether the device is a master or slave. bit 6: spen , spi enabl e . 0: t he spi interface is disabled and all spi pins will be general - purpose i/o ports. 1: t he spi is enabled. bit 5: dord , spi data order . 0: the msb of the data byte is transmitted first. 1: the lsb of the data byte is transmitted first. bit 4: mstr , m aster/slave mode select 0: selects slave spi mode. 1: selects master spi mode. bit 3: cpol , spi clock polarity select 0: spiclk is low when idle. the leading edge of spiclk is the rising edge and the trailing edge is the falling edge. 1: spiclk is high wh en idle. the leading edge of spiclk is the falling edge and the trailing edge is the rising edge. bit 2: cpha , spi clock phase select 0 : data is driven when /ss pin is low (ssig=0) and changes on the trailing edge of spiclk. data is sampled on the leading edge of spiclk. 1: data is driven on the leading edge of spiclk, and is sampled on the trailing edge. bit 1~0: spr1 - spr0 , spi c lock rate select 0 & 1 (associated with spr2, when in master mode) spr 2 spr1 spr0 spi clock selection spi clock rate @ sysclk = 1 2mhz spi clock rate @ sysclk = 48 mhz 0 0 0 sysclk/ 4 3 mhz 12 mhz 0 0 1 sysclk/8 1.5 mhz 6 mhz 0 1 0 sysclk/16 750 khz 3 m hz 0 1 1 sysclk/32 375 khz 1.5 mhz 1 0 0 sysclk/64 187.5 khz 750 khz 1 0 1 sysclk/128 93.75 khz 375 khz 1 1 0 s1tof/6 variable var iable 1 1 1 t0of/6 variable variable note: 1. sysclk is the system clock . 2. s1tof is uart1 baud - rate generator overflow. 3. t 0 of is timer 3 overflow.
megawin mg82fg5b xx data sheet 167 spstat: spi status register sfr page = 0~f sfr address = 0x84 reset= 0000 - 0 xx0 7 6 5 4 3 2 1 0 spif wcol thrf spibsy modf -- -- spr2 r /w r /w r r w w w r/w bit 7: spif , spi transfer completion flag 0: the spif is cleared in software by writing ? 1 ? to this bit. 1: when a serial transfer finishes, the spif bit is set and an interrupt is generated i f spi interrupt is enabled. if n ss pin is driven low when spi is in master mode with ssig=0, spif will also be set to signal the ?mode change?. bit 6: wcol , spi write collision flag. 0: the wcol flag is cleared in software by writing ? 1 ? to this bit. 1: the wcol bit is set if the spi data register, spdat, is written during a data transfer (see section ? 20.2.5 write collision ? ). bit 5: thr f, transmit holding register ( t hr) full flag. read only. 0: m eans the thr is ?empty?. this bit is cleared by hardware when the thr is empty. that means the data in thr is loaded (by h/w) into the output shift register to be transmitted, and now the user can write the next data byte to s pdat for next transmission. 1: m eans the thr is ? full ?. this bit is set by hardware just when spdat is written by software. bit 4, spibsy, spi busy flag. read only. 0: it indicates spi engine is idle and all shift registers are empty. 1: it is set to logi c 1 when a spi transfer is in progress (master or slave mode). bit 3: mode fault flag. (under verify) bit 2 ~1: reserved. software must write ? 0 ? on these bits when spstat is written. bit 0: spr2 , spi clock rate select 2 (associated with spr1 and spr0) . spdat: spi data register sfr page = 0~f sfr address = 0x86 reset= 0000 - 0000 7 6 5 4 3 2 1 0 (msb) (lsb) r /w r /w r /w r/w r /w r /w r/w r/w spdat has two physical buffers for writing to and reading from during transmit and receive, respectively. auxr1 : auxiliary control register 1 sfr page = 0~f sfr address = 0xa2 reset = 0000 - 0000 7 6 5 4 3 2 1 0 p1kbih p3kbil p4spi p3s1 p3s1mi p6twi p3cex dps r/w r/w r/w r/w r /w r /w r /w r/w bit 5: p4spi, spi interface on p4.1~p4.0 and p2.1~p2.0. p4spi nss mosi miso spiclk 0 p1.4 p1.5 p1.6 p1.7 1 p2.0 p2.1 p4.1 p4.0
168 mg82fg5b xx data sheet megawin 20.5. spi sample code (1). required function: set spi master write/read assembly code example: mov sp con,#( spen | ssig | mstr) ;enable spi and set sampling data at rising edge, ; spic lk is sysclk/ 4. mov p1 m 0 ,#0 b0 h ; set p14 to push - pull clr p14 ; enable slave device select mov spdat ,# 55 h ; spi send addr=0x55 to slave mov a ,# 2 0h check_thrf_0: anl a,spstat jnz check_thrf_0 mov spdat ,# 0aa h ; spi send data=0xaa to slave; mov a ,# 1 0h check_spibsy_0: anl a,spstat jnz check_spibsy_0 setb p14 ; disable slave device select clr p14 ; enable slave device select mov spdat ,# 55 h ; spi send addr=0x55 to slave mov a ,# 2 0h check_thrf_0: anl a,spstat jnz check_thrf_0 mov spdat ,# 0ff h ; spi send data=0xff dummy data, and read back data mov a ,# 1 0h check_spibsy_0: anl a,spstat jnz check_spibsy_0 setb p14 ; disable slave device select mov a,spdat ;spdat=read back data c cod e example: #define ncs p14 void main(void) { unsigned char spi_read_data; spcon = ( spen | ssig | mstr); //enable spi and set sampling data at rising edge, spiclk is sysclk / 4. p1m0 = 0xb0; //set p14 to push - pull ncs = 0; //enable slave device select spdat = 0x55; // spi send addr=0x55 to slave; while(spstat & thrf); spdat = 0xaa; //spi send data=0xaa to slave; while(spstat & spibsy); ncs = 1; //disable slave device select //; ncs = 0; //enable slave device select spdat = 0x55; // spi send addr=0x55 to slave; while(spstat & thrf); spdat = 0xff; // s pi send data=0xff dummy data, and read back data while(spstat & spibsy); ncs = 1; //disable slave device select spi_read_data = spdat; while (1); }
megawin mg82fg5b xx data sheet 169 21. two wire serial interface (twi 0 and twi 1 ) the two - wire serial interface is a two - wire, bi - directional serial bus. it is ideally suited for typical microcontroller applications. the mg82fg5bxx is embedded two independent hardware engine to service the two - wire serial interface, twi 0 and twi1. twi 1 is duplicated design from twi 0 with fully compatible control flow except different sfr access page and different port pin. all twi 0 sfrs are accessed in sfr page 0 and its interface pins are twi 0 _scl and twi 0 _sda. the sfrs of twi1 are located in sfr page 1 with the two signals, twi1_scl and twi1_sda. the twi 0 protocol allows the systems designer to interconnect up to 128 different devices using only two bi - directional bus lines, one for clock ( twi0_ scl) and one for data ( twi0_ sda). the twi 0 bus provides control of twi0_ sda (serial data), twi0_ scl (serial clock) generation and synchronization, arbitration logic, and start/stop control and generation. the only external hardware needed to implement th is bus is a single pull - up resistor for each of the twi 0 b us lines. all devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the twi 0 protocol. figure 21? 1 . twi 0 bus interconnection device 0 device 1 device 2 device n twi 0 _ sda twi 0 _ scl vdd C
170 mg82fg5b xx data sheet megawin 21.1. o perating modes the re are four operating modes for the twi 0 : 1) master /t ransmitter mode , 2) master / receiver mode , 3) slave/transmitter mode and 4) slave/receiver mode . bits sta, sto and aa in sicon decide the next action which the twi 0 hardware will take after si is cleared by software . when the next action is completed, a new status code in sista will be updated and si will be set by hardware in the same time. now, the interrupt service routine is entered (if the twi 0 interrupt is enabled), and the new status code can be used to de termine which appropriate routine the s oftware is to branch to . 21.1.1. master transmitter mode in the master transmitter mode, a number of data bytes are tra nsmitted to a slave receiver. before the master transmitter mode can be entered, s i con must be initialized as follows: sicon 7 6 5 4 3 2 1 0 cr2 ensi sta sto si aa cr1 cr0 bit rate 1 0 0 0 x bit rate cr0, cr1, and cr2 define the serial bit rate. ens i must be set to logic 1 to enable twi 0 . if the aa bit is reset, twi 0 will not acknowledge its own slave address or the general call address in the event of another device b ecoming master of the bus. in other words, if aa is reset, twi 0 cannot enter a slave mode. sta, sto, and si must be reset. the master transmitter mode may now be enter ed by software setting t he sta bit. the twi 0 logic will now test the serial bus and generate a start condition as soon as the bus becomes free. when a start condition is tra nsmitted, the serial interrupt flag (si) is set, and the status code in the status register (s i sta) will be 08h. this status code must be used to vector to an interrupt service routine that loads sidat with the slave address and the data direction bit (sla +w). the si bit in sicon must then be reset before the serial transfer can continue. when the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (si) is set again, and a number of status codes in sista are possible. there are 18h, 20h, or 38h for the master mode and also 68h, 78h, or b0h if the slave mode was enabled (aa=1). the appropriate action to be taken for each of these status codes is detailed in the following operating f low chart . after a repeated start condition (state 10h), twi 0 may switch to the master receiver mode by loading sidat with sla+r. 21.1.2. master receiver mode in the master receiver mode, a number of data bytes are received from a slave transmitter. s i con must b e initialized as in the master transmitter mode. when the start condition has been transmitted, the interrupt service routine must load sidat with the 7 - bit slave address and the data direction bit (sla+r). the si bit in s i con must then be cleared before t he serial transfer can continue. when the slave address and the data direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (si) is set again, and a number of status codes in s i sta are possible. the y are 40h, 48h, or 38h for the master mode and also 68h, 78h, or b0h if the slave mode was enabled (aa=1). the appropriate action to be taken for each of these status codes is detailed in the following operating flow chart . after a repeated start condition (sta te 10h), twi 0 may switch to the master transmitter mode by loading sidat with sla+w.
megawin mg82fg5b xx data sheet 171 21.1.3. slave transmitter mode in the slave transmitter mode, a number of data bytes are transmitted to a master receiver. to initiate the slave transmitter mode, s i adr and s i con must be loaded as follows: siadr 7 6 5 4 3 2 1 0 x x x x x x x gc | < - - ----------------- ------- ---- own slave address -------------------- ---- >| the upper 7 bits are the address to which twi 0 will respond when addressed by a master. if the lsb (gc) is set, twi 0 will respond to the general call address (00h); otherwise it ignores the general call address. sicon 7 6 5 4 3 2 1 0 cr2 ensi sta sto si aa cr1 cr0 x 1 0 0 0 1 x x cr0, cr1, and cr2 do not affect twi 0 in the slave mode. ensi must be set to ?1? to enable twi 0 . the aa bit must be set to enable twi 0 to acknowledge its own slave address or the general call address. sta, sto, and si must be cleared to ? 0 ?. when s i adr and sicon have been initialized, twi 0 waits until it is addressed by its own slave address followed by the data direction bit which must be ?1? (r) for twi 0 to operate in the slave transmitter mode. after its own slave address and the ?r? bit have been received, the serial interrupt flag (si) is set and a valid status code can be read from sista. this status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status codes is detailed in the following operating flow chart . the slave transmitter mode may also be entered if arbitration is lost while twi 0 is in the master mode (see state b0h). if the aa bit is reset during a transfer, twi 0 will transmit the last byte of the transfer and enter state c0h or c8h. twi 0 is switched to the not - addressed slave mode and will ignore t he master receiver if it continues the transfer. thus the master receiver receives all 1s as serial data. while aa is reset, twi 0 does not respond to its own slave address or a general call address. however, the serial bus is still monitored, and address r ecognition may be resumed at any time by setting aa. this means that the aa bit may be used to temporarily isolate twi 0 from the bus . 21.1.4. slave receiver mode in the slave receiver mode, a number of data bytes are received from a master transmitter. data tran sfer is initialized as in the slave transmitter mode. when siadr and sicon have been initialized, tw 0 i waits until it is addressed by its own slave address followed by the data direction bit which must be ?0? (w) for twi 0 to operate in the slave receiver mode. after its own slave address and the w bit have been received, the serial interrupt flag ( s i) is set and a valid status code can be read from sista. this status code is used to vector to an interrupt service routine, and the appropriate action to be t aken for each of these status codes is detailed in the following operating flow chart . the slave receiver mode may also be entered if arbitration is lost while tw 0 i is in the master mode (see status 68h and 78h). if the aa bit is reset during a transfer, twi 0 will return a not acknowledge (logic 1) to sda after the next received data byte. while aa is reset, twi 0 does not respond to its own slave address or a general call address. however, the serial bus is still monitored and address recognition may be re sumed at any time by setting aa. this means that the aa bit may be used to temporarily isolate from the bus.
172 mg82fg5b xx data sheet megawin 21.2. m iscellaneous states there are two sista codes that do not correspond to a defined twi 0 hardware state , as described below . s1sta = f8h: this status code indicates that no relevant information is available because the serial interrupt flag, si, is not yet set. this occurs between other states and when twi 0 is not involved in a serial transfer. s1sta = 00h: this status code indicates that a bus error has occurred during an twi 0 serial transfer. a bus error is caused when a start or stop condition occurs at an illegal position in the format frame. examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. a bus error may also be caused when external interference disturbs the internal twi 0 signals. when a bus error occurs, si is set. to recover from a bus error, the sto flag must be set and si must be cleared by software . this causes twi 0 to enter the ?not - addressed? slave mode (a defined state) and to clear the sto flag (no other bits in sicon are affected). the twi0_ sda and twi0_ scl lines are released (a stop condition is not transmitted). 21.3. using the twi 0 the twi 0 is byte - oriented and interrupt based. interrupts are issued after all bus events, like reception of a byte or transmission of a start condition. because the twi 0 is interrupt - based, the application software is free to carry on other operations during a twi 0 byte transfer. note that the twi 0 interrupt enable bit etwi 0 bit ( e ie 1 .6) together with the ea bit allow the application to decide whether or not assertion of the si flag should generate an interrupt request. when the si flag is asserted, the twi 0 has finished an operation a nd awaits application response. in this case, the status register sista contains a status code indicating the current state of the twi 0 bus. the application software can then decide how the twi 0 should behave in the next twi 0 bus operation by properly prog ramming the sta, sto and aa bits (in sicon). the following operating flow charts will instruct the user to use the twi 0 using state - by - state operation. first, the user should fill siadr with its own slave address (refer to the previous description about s iadr). to act as a master, after initializing the sicon, the first step is to set ?sta? bit to generate a start condition to the bus. to act as a slave, after initializing the sicon, the twi 0 waits until it is addressed. and then follow the operating flow chart for a number a next actions by properly programming (sta,sto,si,aa) in the sicon. since the twi 0 hardware will take next action when si is just cleared, it is recommended to program (sta,sto,si,aa) by two steps, first sta, sto and aa, then clear si b it (may use instruction ?clr si?) for safe operation. ? don ? t care ? the figure below shows how to read the flow charts. set sta to generate a start 08h a start has been transmitted the status code in sista, it is the current bus state. the twsi bus operation has just finished. (sta,sto,si,aa)=(0,0,0,x) setting for the next bus operation. "x" means "don't care". sla+w will be transmitted; ack bit will be received. the expected next bus operation.
megawin mg82fg5b xx data sheet 173 c set sta to generate a start 08 h a start has been transmitted from slave mode ( sta , sto , si , aa )=( 0 , 0 , 0 , x ) sla + w will be transmitted ; ack bit will be received . ( 1 ) master / transmitter mode b from master / receiver 18 h sla + w will be transmitted ; ack bit will be received . or 20 h sla + w will be transmitted ; not ack bit will be received . ( sta , sto , si , aa )=( 0 , 0 , 0 , x ) data byte will be transmitted ; ack bit will be received . ( sta , sto , si , aa )=( 1 , 0 , 0 , x ) a repeated start will be transmitted . ( sta , sto , si , aa )=( 0 , 1 , 0 , x ) a stop will be transmitted ; sto flag will be re set . ( sta , sto , si , aa )=( 1 , 1 , 0 , x ) a stop followed by a start will be transmitted ; sto flag will be re s e t . send a stop send a stop followed by a start a repeated start has been transmitted . 28 h data byte in sidat has been transmitted ; ack has be en received . or 30 h data byte in sidat has been transmitted ; not ack has be en received . ( sta , sto , si , aa )=( 0 , 0 , 0 , x ) sla + r will be transmitted ; ack will be received ; twsi will be switched to master / receiver mode a to master / receiver 10 h arbitration lost in sla + w or data bytes 38 h ( sta , sto , si , aa )=( 1 , 0 , 0 , x ) a start will be transmitted when the bus becomes free . ( sta , sto , si , aa )=( 0 , 0 , 0 , x ) the bus will be released ; not addressed slave mode will be entered . enter naslave send a start when bus becomes free
174 mg82fg5b xx data sheet megawin (2) master/receiver mode (sta,sto,si,aa)=(0,0,0,x) sla+r will be transmitted; ack will be received. 50h data byte has been received; ack has been returned. sla+r has been transmitted; ack has been received. 40h from master/transmitter to master/transmitter 58h data byte has been received; not ack has been returned. sla+r has been transmitted; not ack has been received. 48h set sta to generate a start. 08h a start has been transmitted. 38h arbitration lost in sla+r or not ack bit. (sta,sto,si,aa)=(0,0,0,x) the bus will be released; not addressed slv mode will be entered. enter naslave (sta,sto,si,aa)=(1,0,0,x) a start will be transmitted when the bus becomes free. send a start when bus becomes free (sta,sto,si,aa)=(0,0,0,0) data byte will be received; not ack will be returned. (sta,sto,si,aa)=(0,0,0,1) data byte will be received; ack will be returned. 10h a repeated start has been transmitted. (sta,sto,si,aa)=(0,0,0,x) sla+w will be transmitted; ack will be received; twsi will be switched to mst/trx mode. (sta,sto,si,aa)=(1,0,0,x) a repeated start will be transmitted. (sta,sto,si,aa)=(0,1,0,x) a stop will be transmitted; sto flag will be reset. (sta,sto,si,aa)=(1,1,0,x) a stop followed by a start will be transmitted; sto flag will be reset. send a stop send a stop followed by a start from slave mode c b a
megawin mg82fg5b xx data sheet 175 (3) slave/transmitter mode a8h own sla+r has been received; ack has been returned. b0h arbitration lost in sla+r/w as master; own sla+r has been received; ack has been returned. or c8h last data byte in sidat has been transmitted; ack has been received. b8h data byte in sidat has been transmitted; ack has been received. c0h data byte or last data byte in sidat has been transmitted; not ack has been received. (sta,sto,si,aa)=(0,0,0,1) data byte will be transmitted; ack will be received. (sta,sto,si,aa)=(0,0,0,0) last data byte will be transmitted; ack will be received. (sta,sto,si,aa)=(0,0,0,1) data byte will be transmitted; ack will be received. (sta,sto,si,aa)=(0,0,0,0) last data byte will be transmitted; ack will be received. set aa (sta,sto,si,aa)=(1,0,0,1) switch to not addressed slv mode; own sla will be recognized; a start will be transmitted when the bus becomes free. (sta,sto,si,aa)=(1,0,0,0) switch to not addressed slv mode; no recognition of own sla; a start will be transmitted when the bus becomes free. (sta,sto,si,aa)=(0,0,0,1) switch to not addressed slv mode; own sla will be recognized. (sta,sto,si,aa)=(0,0,0,0) switch to not addressed slv mode; no recognition of own sla. ` enter naslave send a start when bus becomes free to master mode c
176 mg82fg5b xx data sheet megawin 88h data byte has been received; not ack has been returned. 60h own sla+w has been received; ack has been returned. 68h arbitration lost in sla+r/w as master; own sla+w has been received; ack has been returned. or (4) slave/receiver mode a0h a stop or repeated start has been received while still addressed as slv/rec. 80h data byte has been received; ack has been returned. (sta,sto,si,aa)=(0,0,0,0) data will be received; not ack will be returned. (sta,sto,si,aa)=(0,0,0,1) data byte will be received; ack will be returned. (sta,sto,si,aa)=(0,0,0,0) data byte will be received; not ack will be returned. set aa (sta,sto,si,aa)=(1,0,0,1) switch to not addressed slv mode; own sla will be recognized; a start will be transmitted when the bus becomes free. (sta,sto,si,aa)=(1,0,0,0) switch to not addressed slv mode; no recognition of own sla; a start will be transmitted when the bus becomes free. (sta,sto,si,aa)=(0,0,0,1) switch to not addressed slv mode; own sla will be recognized. (sta,sto,si,aa)=(0,0,0,0) switch to not addressed slv mode; no recognition of own sla. ` enter naslave send a start when bus becomes free to master mode (sta,sto,si,aa)=(0,0,0,1) data will be received; ack will be returned. c
megawin mg82fg5b xx data sheet 177 98h previously addressed with general call address; data byte has been received; not ack has been returned. 70h general call address has been received; ack has been returned. 78h arbitration lost in sla+r/w as master; general call address has been received; ack has been returned. or (5) slave/receiver mode (for general call) a0h a stop or repeated start has been received while still addressed as slv/rec. 90h previously addressed with general call address; data byte has been received; ack has been returned. (sta,sto,si,aa)=(0,0,0,0) data will be received; not ack will be returned. (sta,sto,si,aa)=(0,0,0,1) data byte will be received; ack will be returned. (sta,sto,si,aa)=(0,0,0,0) data byte will be received; not ack will be returned. set aa (sta,sto,si,aa)=(1,0,0,1) switch to not addressed slv mode; own sla will be recognized; a start will be transmitted when the bus becomes free. (sta,sto,si,aa)=(1,0,0,0) switch to not addressed slv mode; no recognition of own sla; a start will be transmitted when the bus becomes free. (sta,sto,si,aa)=(0,0,0,1) switch to not addressed slv mode; own sla will be recognized. (sta,sto,si,aa)=(0,0,0,0) switch to not addressed slv mode; no recognition of own sla. ` enter naslave send a start when bus becomes free to master mode (sta,sto,si,aa)=(0,0,0,1) data will be received; ack will be returned. c
178 mg82fg5b xx data sheet megawin 21.4. twi 0 register siadr: 2 - wire serial int erface address register sfr page = 0 only sfr address = 0xd1 reset= 0000 - 0000 7 6 5 4 3 2 1 0 a6 a5 a4 a3 a2 a1 a0 gc r /w r /w r /w r/w r /w r /w r/w r/w the cpu can read from and write to this register directly . s ia dr is not affected by the twi 0 hardwa re. the contents of this register are irrelevant when tw i 0 is in a master mode. in the slave mode, the seven most significant bits must be loaded with the microcontroller?s own slave address, and, if the least significant bit (gc) is set, the general call address (00h) is recognized; otherwise it is ignored. the most significant bit corresponds to the first bit received from the twi 0 bus after a start condition. sidat: 2 - wire serial interface data register sfr page = 0 only sfr address = 0xd2 reset= 00 00- 0000 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 r /w r /w r /w r/w r /w r /w r/w r/w this register contains a byte of serial data to be transmitted or a byte which has just been received. the cpu can read from or write to this register directly while it is not in the process of shifting a byte. this occurs when twi 0 is in a defined state and the serial interrupt flag (si) is set. data in s i dat remains stable as long as si is set. while data is being shifted out, data on the bus is simultaneously being shifte d in; sidat always contains the last data byte present on the bus. thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in s i dat. s i dat and the ack flag form a 9 - bit shift register which shifts in or shifts out an 8 - bit byte, followed by an acknowledge bit. the ack flag is controlled by the twi 0 hardware and cannot be accessed by the cpu. serial data is shifted through the ack flag into sidat on the rising edges of serial clock pulse s on the twi 0 _ scl line. when a byte has been shifted into sidat, the serial data is available in s i dat, and the acknowledge bit is returned by the control logic during the 9th clock pulse. serial data is shifted out from sidat on the falling edges of clock pulses on the twi 0 _ scl line. when the cpu writes to s i dat, the bit sd7 is the first bit to be transmitted to the twi 0 _ sda line. after nine serial clock pulses, the eight bits in sidat will have been transmitted to the twi0_ sda line, and the acknowledge b it will be present in the ack flag . note that the eight transmitted bits are shifted back into sidat. sicon: 2 - wire serial interface control register sfr page = 0 only sfr address = 0xd4 reset= 0000 - 0000 7 6 5 4 3 2 1 0 cr2 ensi sta sto si aa cr1 cr0 r /w r /w r /w r/w r /w r /w r/w r/w the cpu can read from and write to this register directly . two bits are affected by the twi 0 hardware: the si bit is set when a serial interrupt is requested, and the sto bit is cleared when a stop condition is present o n the bus. the sto bit is also cleared when ens i ="0". bit 7: c r2 , twi 0 c lock r ate sele ct bit 2 (associated with c r1 and c r0) . bit 6 : ens i , the twi 0 hardware enable bit when ensi is "0", the twi 0 _ sda and twi 0 _ scl outputs are in a high impedance state. twi 0 _ sda and twi 0 _ scl input signals are ignored, twi 0 is in the not - addressed slave state, and sto bit in sicon is forced to "0". no other bits are affected, and, twi 0 _ sda and twi 0 _ scl assigned port pins may be used as general purpose i/o pins. when ensi is " 1", tw i 0 is enabled, and, t he twi 0 _ sda and twi 0 _ scl assigned port pin
megawin mg82fg5b xx data sheet 179 latches , such p4.1 and p4.0, must be set to logic 1 and i/o mode must be configured to open - drain mode for the following serial communication . bit 5 : sta, the start flag when the sta bi t is set to enter a master mode, the twi 0 hardware checks the status of the serial bus and generates a start condition if the bus is free. if the bus is not free, then twi 0 waits for a stop condition and generates a start condition after a delay. if sta is set while twi 0 is already in a master mode and one or more bytes are transmitted or received, twi 0 transmits a repeated start condition. sta may be set at any time. sta may also be set when twi 0 is an addressed slave. when the sta bit is reset, no start c ondition or repeated start condition will be generated. bit 4 : sto, the stop flag when the sto bit is set while twi 0 is in a master mode, a stop condition is transmitted to the serial bus. when the stop condition is detected on the bus, the twi 0 hardware clears the sto flag. in a slave mode, the sto flag may be set to recover from a bus error condition. in this case, no stop condition is transmitted to the bus. however, the twi 0 hardware behaves as if a stop condition has been received and switches to the defined not addressed slave receiver mode. the sto flag is automatically cleared by hardware. if the sta and sto bits are both set, then a stop condition is transmitted to the bus if twi 0 is in a master mode (in a slave mode, twi 0 generates an internal sto p condition which is not transmitted), and then transmits a start condition. bit 3 : si, the serial interrupt flag when a new twi 0 state is present in the s i sta register, the si flag is set by hardware. a nd, if the twi 0 interrupt is enabled , a n interrupt s ervice routine will be serviced . the only state that does not cause si to be set is state f8h, which indicates that no relevant state information is available. when si is set, the low period of the serial clock on the twi 0 _ scl line is stretched, and the se rial transfer is suspended. a high level on the twi 0 _ scl line is unaffected by the serial interrupt flag. si must be cleared by soft ware writing ? 0 ? on this bit . whe n the si flag is reset, no serial interrupt is requested, and there is no stretching on the serial clock on the twi 0 _ scl line. bit 2: aa, the assert acknowledge flag if the aa flag is set to ? 1 ?, an acknowledge (low level to twi 0 _ sda) will be returned during the acknowledge clock pulse on the twi 0 _ scl line when: 1) the own slave address has bee n received. 2) a data byte has been received while twi 0 is in the master / receiver mode. 3) a data byte has been received while twi 0 is in the addressed slave / receiver mode. if the aa flag is reset to ? 0 ?, a not acknowledge (high level to twi 0 _ sda) will be returned during the acknowledge clock pulse on twi 0 _ scl when: 1) a data has been received while twi 0 is in the master / receiver mode. 2) a data byte has been received while twi 0 is in the addressed slave / receiver mode. bit 7, 1~0: cr2 , cr1 and cr 0 , the cl ock rate select bits these three bits determine the serial clock frequency when twi 0 is in a master mode. the clock rate is not important when twi 0 is in a slave mode because twi 0 will automatically synchronize with any clock frequency , which is from a mas ter, up to 100khz. the various serial clock rates are shown in table 21 ? 1 . table 21 ? 1 . twi 0 serial clock rates c r 2 c r1 c r0 twi 0 clock selection twi 0 clock rate @ sysc lk =12mhz 0 0 0 sysclk/8 1.5 mhz 0 0 1 sysclk/16 750 khz 0 1 0 sysclk/32 3 75 khz 0 1 1 sysclk/64 187.5 khz 1 0 0 sysclk/128 93.75 khz 1 0 1 sysclk/256 46 . 8 75 khz 1 1 0 s1tof/ 6 variable 1 1 1 t0of/6 variable note: 1. sysclk is the system clock .
180 mg82fg5b xx data sheet megawin 2. s1tof is uart1 baud - rate generator overflow. 3. t 0 of is timer 0 overflow. sista: 2 - wire serial interface status register sfr page = 0 only sfr address = 0xd3 reset= 1111 - 1000 7 6 5 4 3 2 1 0 sis7 sis6 sis5 sis4 sis3 sis2 sis1 sis0 r r r r r r r r sista is an 8 - bit read - only register. the three least significant bits are always 0. the five most significant bits contain the status code. there are a number of p ossible status codes. when s i sta contains f8h, no serial interrupt is requested. all other s ista values correspond to defined twi 0 states. when each of these states is entered, a status interrupt is requested (si=1). a valid status code is present in sista when si is set by hardware . in addition, state 00h stands for a bus error. a bus error occ urs when a start or stop condition is present at an illegal position , such as inside an address /data byte or just on an acknowledge bit . auxr1 : auxiliary control register 1 sfr page = 0~f sfr address = 0xa2 reset = 0000 - 0000 7 6 5 4 3 2 1 0 p1kbih p3 kbil p4spi p3s1 p3s1mi p6twi 0 p3cex dps r/w r/w r/w r/w r /w r /w r /w r/w bit 2: p6twi 0 , twi 0 function on p6. the function is valid when p60oc[1:0] is equal to ? 00? . p6twi twi 0 _scl twi 0 _sda 0 p4.0 p4.1 1 p6.0 p6.1
megawin mg82fg5b xx data sheet 181 21.5. twi1 register si1adr: 2 - wire ser ial interface 1 address register sfr page = 1 only sfr address = 0xd1 reset= 0000 - 0000 7 6 5 4 3 2 1 0 a61 a51 a41 a31 a21 a11 a01 gc1 r /w r /w r /w r/w r /w r /w r/w r/w the cpu can read from and write to this register directly . s i 1 a dr is not affected by the twi 1 hardware. the contents of this register are irrelevant when tw i 1 is in a master mode. in the slave mode, the seven most significant bits must be loaded with the microcontroller?s own slave address, and, if the least significant bit (gc 1 ) is set , the general call address (00h) is recognized; otherwise it is ignored. the most significant bit corresponds to the first bit received from the twi 1 bus after a start condition. si1dat: 2 - wire serial interface 1 data register sfr page = 1 only sfr addre ss = 0xd2 reset= 0000 - 0000 7 6 5 4 3 2 1 0 d71 d61 d51 d41 d31 d21 d11 d01 r /w r /w r /w r/w r /w r /w r/w r/w this register contains a byte of serial data to be transmitted or a byte which has just been received. the cpu can read from or write to this register directly while it is not in the process of shifting a byte. this occurs when twi 1 is in a defined state and the serial interrupt flag (si 1 ) is set. data in s i 1 dat remains stable as long as si 1 is set. while data is being shifted out, data on the b us is simultaneously being shifted in; si 1 dat always contains the last data byte present on the bus. thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in s 1 i dat. s i 1 dat and the a ck flag form a 9 - bit shift register which shifts in or shifts out an 8 - bit byte, followed by an acknowledge bit. the ack flag is controlled by the twi 1 hardware and cannot be accessed by the cpu. serial data is shifted through the ack flag into si 1 dat on t he rising edges of serial clock pulses on the twi1_ scl line. when a byte has been shifted into si 1 dat, the serial data is available in s i 1 dat, and the acknowledge bit is returned by the control logic during the 9th clock pulse. serial data is shifted out f rom si 1 dat on the falling edges of clock pulses on the twi1_ scl line. when the cpu writes to s i 1 dat, the bit d7 1 is the first bit to be transmitted to the twi1_ sda line. after nine serial clock pulses, the eight bits in si 1 dat will have been transmitted t o the twi1_ sda line, and the acknowledge bit will be present in the ack flag . note that the eight transmitted bits are shifted back into si 1 dat. si 1 con: 2 - wire serial interface 1 control register sfr page = 1 only sfr address = 0xd4 reset= 0000 - 0000 7 6 5 4 3 2 1 0 cr21 ensi1 sta1 sto1 si1 aa1 cr11 cr01 r /w r /w r /w r/w r /w r /w r/w r/w the cpu can read from and write to this register directly . two bits are affected by the twi 1 hardware: the si 1 bit is set when a serial interrupt is requested, and th e sto 1 bit is cleared when a stop condition is present on the bus. the sto 1 bit is also cleared when ens i1 ="0". bit 7: c r2 1, twi1 c lock r ate sele ct bit 2 (associated with c r1 1 and c r0 1 ) . bit 6 : ens i 1 , the twi 1 hardware enable bit when ensi 1 is "0", the t wi1_ sda and twi1_ scl outputs are in a high impedance state. twi1_ sda and twi1_ scl input signals are ignored, twi 1 is in the not - addressed slave state, and sto 1 bit in si 1 con is forced to "0". no other bits are affected, and, twi1_ sda and twi1_ scl assigned port pins may be used as general purpose i/o pins. when ensi 1 is "1", tw i 1 is enabled, and, t he twi1_ sda and twi1_ scl assigned port pins
182 mg82fg5b xx data sheet megawin latches , such as p1.1 and p1.0, must be set to logic 1 and i/o mode must be configured to open - drain mode for the follo wing serial communication . bit 5 : sta 1 , the start flag when the sta 1 bit is set to enter a master mode, the twi 1 hardware checks the status of the serial bus and generates a start condition if the bus is free. if the bus is not free, then twi 1 waits for a stop condition and generates a start condition after a delay. if sta 1 is set while twi 1 is already in a master mode and one or more bytes are transmitted or received, twi 1 transmits a repeated start condition. sta 1 may be set at any time. sta 1 may also be set when twi 1 is an addressed slave. when the sta 1 bit is reset, no start condition or repeated start condition will be generated. bit 4 : sto 1 , the stop flag when the sto 1 bit is set while twi 1 is in a master mode, a stop condition is transmitted to the serial bus. when the stop condition is detected on the bus, the twi 1 hardware clears the sto 1 flag. in a slave mode, the sto 1 flag may be set to recover from a bus error condition. in this case, no stop condition is transmitted to the bus. however, the twi 1 hardware behaves as if a stop condition has been received and switches to the defined not addressed slave receiver mode. the sto 1 flag is automatically cleared by hardware. if the sta 1 and sto 1 bits are both set, then a stop condition is transmitted to t he bus if twi 1 is in a master mode (in a slave mode, twi 1 generates an internal stop condition which is not transmitted), and then transmits a start condition. bit 3 : si 1 , the serial interface 1 interrupt flag when a new twi 1 state is present in the s i 1 st a register, the si 1 flag is set by hardware. a nd, if the twi 1 interrupt is enabled , a n interrupt service routine will be serviced . the only state that does not cause si to be set is state f8h, which indicates that no relevant state information is available . when si 1 is set, the low period of the serial clock on the twi1_ scl line is stretched, and the serial transfer is suspended. a high level on the twi1_ scl line is unaffected by the serial interrupt flag. si 1 must be cleared by soft ware writing ? 0 ? on this bit . whe n the si 1 flag is reset, no serial interrupt is requested, and there is no stretching on the serial clock on the twi1_ scl line. bit 2: aa 1 , the assert acknowledge flag if the aa 1 flag is set to ? 1 ?, an acknowledge (low level to twi1_s da) will be returned during the acknowledge clock pulse on the twi1_ scl line when: 1) the own slave address has been received. 2) a data byte has been received while twi 1 is in the master / receiver mode. 3) a data byte has been received while twi 1 is in the addressed s lave / receiver mode. if the aa 1 flag is reset to ? 0 ?, a not acknowledge (high level to twi1_ sda) will be returned during the acknowledge clock pulse on twi1_ scl when: 1) a data has been received while twi 1 is in the master / receiver mode. 2) a data byte has been received while twi 1 is in the addressed slave / receiver mode. bit 7, 1~0: cr21 , cr1 1 and cr 01 , the clock rate select bits these three bits determine the serial clock frequency when twi 1 is in a master mode. the clock rate is not important when twi 1 i s in a slave mode because twi 1 will automatically synchronize with any clock frequency , which is from a master, up to 100khz. the various serial clock rates are shown in table 21 ? 1 . table 21 ? 2 . twi1 serial clock rates c r 21 c r1 1 c r0 1 twi 1 clock selection twi1 clock rate @ sysclk =12mhz 0 0 0 sysclk/8 1.5 mhz 0 0 1 sysclk/16 750 khz 0 1 0 sysclk/32 3 75 khz 0 1 1 sysclk/64 187.5 khz 1 0 0 sysclk/128 93.75 khz 1 0 1 s ysclk/256 46 . 8 75 khz 1 1 0 s1tof/ 6 variable 1 1 1 t0of/6 variable
megawin mg82fg5b xx data sheet 183 note: 1. sysclk is the system clock . 2. s1tof is uart1 baud - rate generator overflow. 3. t0of is timer 0 overflow. si1sta: 2 - wire serial interface 1 status register sfr page = 1 only sf r address = 0xd3 reset= 1111 - 1000 7 6 5 4 3 2 1 0 sis71 sis61 sis51 sis41 sis31 sis21 sis11 sis01 r r r r r r r r si 1 sta is an 8 - bit read - only register. the three least significant bits are always 0. the five most significant bits contain the status code. there are a number of p ossible status codes. when s i 1 sta contains f8h, no serial interrupt is requested. all other si 1 sta values correspond to defined twi 1 states. when each of these states is entered, a status interrupt is requested (si 1 =1). a vali d status code is present in si 1 sta when s 1 is set by hardware . in addition, state 00h stands for a bus error. a bus error occurs when a start or stop condition is present at an illegal position , such as inside an address /data byte or just on an acknowledg e bit . auxr3: auxiliary register 3 sfr page = 0~f sfr address = 0xa4 reset = 0000 - 0000 7 6 5 4 3 2 1 0 staf stof bpoc1 bpoc0 gf p1s0mi p3eci p3twi1 r/w r/w r/w r/w r/w r/w r/w r/w bit 0: p3twi1, twi1 function on p3. p3twi1 twi1_scl twi1_sda 0 p1. 0 p1.1 1 p3.0 p3.1
184 mg82fg5b xx data sheet megawin 21.6. twi 0 sample code (1). required function: set twi 0 master write/read assembly code example under constructed ? c code example: uchar i2c_read(uchar dev_addr, uchar reg_addr) { uchar usdata = 0; sicon |= sta; sicon &= ~si; while(( sicon & si ) != si ); sicon &= ~sta; sidat = dev_addr; // send device address sicon &= ~si; while(( sicon & si ) != si ); sidat = reg_addr; // send register address sicon &= ~si; while(( sicon & si ) != si ); sicon |= sta; // restart sicon &= ~si; while(( sicon & si ) != si ); sicon &= ~sta; sidat = dev_addr | 0x01; // send device address sicon &= ~si; while(( sicon & si ) != si ); sicon &= ~si; while(( sicon & si ) != si ); usdata = sidat; sicon | = sto; sicon &= ~si; while(( sicon & sto ) == sto ); return usdata; } void i2c_write(uchar dev_addr, uchar reg_addr, uchar ucdata) { sicon |= sta; sicon &= ~si; while(( sicon & si ) != si ); sicon &= ~sta; sidat = d ev_addr; // send device address sicon &= ~si; while(( sicon & si ) != si ); sidat = reg_addr; // send register address sicon &= ~si; while(( sicon & si ) != si ); sidat = ucdata; // send data sicon &= ~si; while(( sicon & si ) != si ); sicon |= sto; sicon &= ~si; while(( sicon & sto ) == sto );
megawin mg82fg5b xx data sheet 185 } void main() { sicon |= ensi ; //enable twi 0 and clock source is 1.5m@mcu run at 12mhz i2c_write(0xa0, 0 x30, 0x55); delay_ms(10); p0 = i2c_read(0xa0, 0x30); while(1); }
186 mg82fg5b xx data sheet megawin 22. serial interface detection (sid / stwi ) the serial interface detection module is always monitoring the ? start ? and ? stop ? condition on software two - wire - interface ( s twi). s twi_scl is the serial clock signal and s twi_sda is the serial data signal. if any matched condition is detected, hardware set the flag on staf and stof. software can poll these two flags or set sidfie (sfie.7) to share the interrupt vector on system flag. and s twi_s cl is located on nint1 which helps mcu to strobe the serial data by nint1 interrupt. software can use these resources to implement a variable twi slave device. 22.1. s id structure figure 22? 1 shows the configuration of staf and stof detection, interrupt architecture and event detecting waveform. figure 22? 1 . serial interface detection structure transition detection stwi _ sda input ( s 0 mi ) stwi _ scl input ( nint 1 ) enable sysclk staf stof auxr 3 . 7 sidfie (sfie.7) sid flags interrupt esf (eie1. 3) auxr3.6 stwi_sda stwi_scl set staf set stof
megawin mg82fg5b xx data sheet 187 22.2. s id register auxr3: auxiliary register 3 sfr page = 0~f sfr address = 0xa4 reset = 0000 - 0000 7 6 5 4 3 2 1 0 staf stof bpoc1 bpoc0 gf p1s0mi p3eci p3twi1 r/w r/w r/w r/w r/w r/w r/w r/w bit 7: staf, start flag detection of s twi. 0: clear by firmware by writing ? 0 ? on it. 1: set by hardware to indicate the start con dition occurred on s twi bus. bit 6: stof, stop flag detection of s twi. 0: clear by firmware by writing ? 0 ? on it. 1: set by hardware to indicate the st op condition occurred on s twi bus. sfie: system flag interrupt enable register sfr page = 0~f sfr addr ess = 0x8e reset = xxxx - x000 7 6 5 4 3 2 1 0 sidfie mcdre mcdfie rtcfie -- bof1ie bof0ie wdtfie r/ w r/w r/w r/w w r/w r/w r/w bit 7: sidfie, serial interface (stwi) detection flag interrupt enabled. 0: disable sid flags (staf or stof) interrupt. 1: enable sid flags (staf or stof) interrupt.
188 mg82fg5b xx data sheet megawin 22.3. sid sample code there are two sample codes in the following diagram to implement s twi slave device. the first one is fully interrupt mode. it uses the staf and stof interrupt to detect the start/stop event and nint interrupt to strobe serial data input. whenn sysclk = 24mhz, the maximum speed of s twi slave is 200k bps. but the real speed must consider the other interrupt service duration in system application. the second sample code is burst mode. software only uses staf and stof for s twi event detection. then, software polls the port pin state for s twi _ scl and s twi _sda control. when sysclk = 24mhz, the general speed is 200k bps in this mode ( 1 ). required function: s twi slave on sysclk=24mhz in fully interrupt mode : assembly code example: $include ( reg_mg8 2 f g 5 b32 . inc) slave_dev_addr equ 20h ; declare slave device address data_length equ 32 ; declare buffer size ; ------------------------------------------------------------------------- ; declare the twsi state ; ------------------------------------------------------------------------- i2c_slavestandby equ 0x00 i2c_sla_with_w equ 0x01 i2c_sla_with_r equ 0x02 i2c_disable equ 0x03 i2c_sl_w_ack equ 0x04 i2c_sl_r_ack equ 0x05 i2c_sl_r_nak equ 0x06 ; ------------------------------------------------------------------------- ; declare the twsi pin ; ------------------------------------------------------------------------- sda equ p3. 2 scl equ p3.3 ; ------------------------------------------------------------------------- ; data area ; ------------------------------------------------------------------------- controldata segment data rseg controldata receivestring: ds data_leng th ; data buffer stack: ds 40 ; stack area size position: ds 1 tempbyte: ds 1 addr: ds 1 iicbyte: ds 1 stage: ds 1 bitdata segment bit rseg bitdata firstby te: dbit 1 ; the flag for receive sla+r/w completeabyte: dbit 1 ; set complete flag when transfer/receive one byte slave_rw: dbit 1 ; clear slave_rw to beceive / set to transfer ; ------------------------------------ ------------------------------------- ; code area ; ------------------------------------------------------------------------- cseg at 0000h ;start address = 0x0000 jmp assembly_main cseg at 0013h ; ex 1 interrupt isr a ddress jmp scl_detect_isr
megawin mg82fg5b xx data sheet 189 cseg at 00 5 bh ; detect staf or stof isr address j mp systemflag_isr twsi_cs segment code rseg twsi_cs using 0 assembly_main: mov sp,#stack ; init ial sp for stack size anl ckcon0,#11111000b ; system clock / 1 call initial_twsi ; initial twsi main_loop: ; to do ... mov acc,stage xrl a,#i2c_disable jz main_loop jnb completeabyte,main_loop ; have a event ? ; ------------------------------------------- mov acc,stage cjne a,#i2c_sla_with_w,subroutine_i2c_sla_with_r subroutine_i2c_sla_with_w: mov r1,# receivestring ; initial for receive clr completeabyte ; clear event flag jmp main_loop subroutine_i2c_sla_with_r: cjne a,#i2c_sla_with_r,subroutine_i2c_sl_w_ack mov r1,#receive string ; initial for transfer mov a,@r1 mov iicbyte,a rlc a ; it must transfer msb to sda mov sda,c clr completeabyte ; clear event flag jmp main_loop subroutine_i2c_sl_w_ack: cjne a,#i2c_sl_w_ack,subroutine_i2c_sl_r_ack mov @r1,iicbyte ; save data to "receivestring" inc r1 ; limit buffer index cj ne r1,#receivestring+data_length,$+3+2 mov r1,#receivestring clr completeabyte ; clear event flag jmp main_loop subroutine_i2c_sl_r_ack: cjne a,#i2c_sl_r_ack,subroutine_i2c_sl_r_ nak inc r1 ; limit buffer index cjne r1,#receivestring+data_length,$+3+2 mov r1,#receivestring mov iicbyte,@r1 ; prepare data form data buffer mov acc,@r1 rlc a mov sda,c ; sda = msb clr completeabyte ; clear event flag jmp main_loop subroutine_i2c_sl_r_nak:
190 mg82fg5b xx data sheet megawin cjne a,#i2c_sl_r_nak,main_loop setb sda ; nak - event clr completeabyte jmp main_loop ; ------------------------------------------------------------------------- ; initial twsi interrupt (priority) & trigger mode ; ------------------------------- ------------------------------------------ initial_twsi: ; system flag have the highest priority orl eip1h,#08h orl eip1l,#08h ; the ex1 priority orl ip0h,#00000100b anl ip0l,#11111011b ; enable etwsi o rl eie1,#esf orl sfie,#sdifie setb ea ; p33 & p3 2 is open drain mode for twsi mov p3m0,# 0c h mov p3m1,# 0c h ; edge detect setb it1 orl auxr0,#int1h ; declare slave device ad dress mov addr,#slave_dev_addr mov stage,#i2c_disable clr completeabyte ret ; ------------------------------------------------------------------------- ; inital twsi's sda (staf & stof) edge detection ; ---------- --------------------------------------------------------------- systemflag_isr: push acc push psw mov acc, auxr1 ; check staf or stof ? jb acc.3,staf_routine jb acc.2,stof_rout ine exit_flag_isr: pop psw pop acc reti staf_routine: ; start of twsi ; initial ex0 for raising edge detection and enable ex0 interrupt orl auxr0, #int1h nop clr ie1 setb sda setb ex1 mov position,#0ffh ; initial position for twsi anl auxr1,#~staf ; clear staf flag clr slave_rw ; clear for receive a byte or address
megawin mg82fg5b xx data sheet 191 mov stage,#i2c_slavestandby setb firstbyte ; address byte flag jmp exit_flag_isr stof_routine: ; stop of tswi clr ex1 ; disable ex0 interupt serv ice routine anl auxr1,#~stof ; clear stof flag mov stage,#i2c_disable jmp exit_flag_isr ; ------------------------------------------------------------------------- ; access sda by ex1 interrupt ; --------------- ---------------------------------------------------------- scl_detect_isr: push acc push psw inc position jb slave_rw,slave_read ; -------------------------------------------------------------------------- slave_ write: mov a,position clr c subb a,#8 jnc slave_write_wait_for_ack ; is ack signal ? slave_write_8bits: ; msb~lsb (8 bits) mov acc,tempbyte ; 1. rotate tempbyte mov c,sda rlc a ; 2. rotate sda to tempbyte.0 mov tempbyte,acc ; mov a,position cjne a,#7,exit_scl_detect_isr ; anl auxr0,#~int1h ; the falling edge o f ack signal nop clr ie1 jmp exit_scl_detect_isr slave_write_wait_for_ack: ; for 9 bit (ack/nak) jnz complete_write_one_byte jnb firstbyte,slave_write_response_ack mov acc,tempb yte clr c rrc a cjne a,addr,not_slave_addr slave_write_response_ack: clr sda jmp exit_scl_detect_isr not_slave_addr: clr ex1 mov stage,#i2c_disable jmp exit_scl_detect_isr complete_write_one_byte: ; 9th falling edge orl auxr0,#int1h ; the raising edge of scl signal nop clr ie1 setb sda setb completeabyte ; set '1' when it receives a byte mov position,#0ffh ; reset position jnb firstbyte,repeat_receive_mode clr firstbyte ; sla+w or sla+r ?
192 mg82fg5b xx data sheet megawin clr slave_rw mov acc,tempbyte jnb acc.0,set_in_slaw_mode setb slave_rw anl auxr0,#~int1h ; the falling edge of ack signal nop clr ie1 mov stage,#i2c_sla_with_r jmp exit_scl_detect_isr set_in_slaw_mode: mov stage,#i2c_sla_with _w jmp exit_scl_detect_isr repeat_receive_mode: mov iicbyte,tempbyte mov stage,#i2c_sl_w_ack ; -------------------------------------------------------------------------- exit_scl_detect_isr: pop psw pop acc reti ; -------------------------------------------------------------------------- slave_read: mov a,position clr c subb a,#7 jnc slave_read_wait_for_ack ; is ack signal ? slave_read_8bits: mo v a,iicbyte ; rotate tempbyte.7 to sda rl a mov iicbyte,a rlc a mov sda,c jmp exit_scl_detect_isr slave_read_wait_for_ack: setb sda jnz complete_read_one_byte jmp exit_scl_detect_isr complete_read_one_byte: setb completeabyte ; set '1' when it receives a byte mov position,#0ffh ; reset position jnb sda,set_i2c_slave_read_ack mov stage,#i2c_sl_r_nak jmp exit_scl_detect_isr set_i2c_slave_read_ack: mov stage,#i2c_sl_r_ack jmp exit_scl_detect_isr ; ----------------------------------------------------------- ------------------------ end c code example: #include #include #define slave_dev_addr 0x20 // declare slave device address #define data_length 32 // declare buffer size
megawin mg82fg5b xx data sheet 193 // ------------- ---------------------------------------------------------------- // declare i2c stage // ----------------------------------------------------------------------------- #define i2c_slavestandby 0x00 #define i2c_sla_with_w 0x01 #define i2c_sla_with_r 0x02 # define i2c_disable 0x03 #define i2c_sl_w_ack 0x04 // sla_ w with data ack #define i2c_sl_r_ack 0x05 // sla_ r with data ack #define i2c_sl_r_nak 0x06 // sla_ r with data nak // ----------------------------------------------------------------------------- // declare global variable // ----------------------------------------------------------------------------- typedef struct { unsigned char addr; unsigned char iicbyte; unsigned char stage:8; unsigned char completeabyte: 1; unsigned char slave_rw:1; } _twsi; _twsi twsi; unsigned char tempbyte; unsigned char position; bit firstbyte; // ----------------------------------------------------------------------------- // declare the twsi pin //------------------------------- ---------------------------------------------- sbit sda = p3^ 2 ; sbit scl = p3^3; // ----------------------------------------------------------------------------- // initial twsi interrupt (priority) & trigger mode //--------------------------------------- -------------------------------------- void initial_twsi () { // system flag have the highest priority eip1h |= 0x08; eip1l |= 0x08; // the ex1 have normal priority ip0h |= 0x08; ip0l &= ~0x08; eie1 |= esf; // enable etwsi sfie |= sdifie ; ea = 1; // p33 & p3 2 is open drain mode for twsi p3m0 = 0x 0c ; p3m1 = 0x 0c ; it1 = 1; auxr0 |= int1h; // declare slave device address twsi.addr = slave_dev_addr; twsi.completeabyte = 0; twsi.stage = i2c_disable; } //-------------------------- --------------------------------------------------- // main() // ----------------------------------------------------------------------------- void main(void) {
194 mg82fg5b xx data sheet megawin unsigned char bufferindex; unsigned char receivestring [data_length]; ckcon0 &= ~0x07; / / system clock / 1 initial_twsi (); // initial interrupt and priority while (1) { if (twsi.stage != i2c_disable) { if (twsi.completeabyte == 1) { switch (twsi.stage) { case i2c_sla_with_w: bufferindex = 0; // initial bufferinde x twsi.completeabyte = 0; twsi.stage = i2c_slavestandby; break; case i2c_sla_with_r: // prepare msb on sda pin twsi.iicbyte = receivestring [0]; sda = twsi.iicbyte & 0x80; bufferindex = 0; // initial bufferind ex twsi.completeabyte = 0; twsi.stage = i2c_slavestandby; break; case i2c_sl_w_ack: receivestring [bufferindex] = twsi.iicbyte; twsi.completeabyte = 0; bufferindex ++; // limit bufferindex 0~31 bufferindex &= 0 x1f; twsi.stage = i2c_slavestandby; break; case i2c_sl_r_ack: bufferindex ++; // limit bufferindex 0~31 bufferindex &= 0x1f; twsi.iicbyte = receivestring [bufferindex]; sda = twsi.iicbyte & 0x80; twsi.comple teabyte = 0; twsi.stage = i2c_slavestandby; break; case i2c_sl_r_nak: sda = 1; twsi.completeabyte = 0; twsi.stage = i2c_slavestandby; break; } } } // to do ... } } //------------------------------------- ---------------------------------------- // inital twsi's sda (staf & stof) edge detection // ----------------------------------------------------------------------------- void systemflag_isr (void) interrupt 11 {
megawin mg82fg5b xx data sheet 195 unsigned char tempreg; tempre g = auxr1; auxr1 &= ~(staf+stof); // clear staf & stof flag if (tempreg & stof) { ex1 = 0; twsi.stage = i2c_disable; } else if (tempreg & staf){ auxr0 |= int1h; // scl raise edge detection _nop_ (); ie1 = 0; sda = 1; ex1 = 1; // enable ex1 position = 0xff; twsi.slave_rw = 0; // clear for receive a byte or address twsi.stage = i2c_slavestandby; firstbyte = 1; } } // ----------------------------------------------------------------------------- // acces s sda by ex1 interrupt // ----------------------------------------------------------------------------- void twsi_ex1_isr (void) interrupt 2 { position ++; if ((twsi.slave_rw) == 0) { if (position < 8) { // 0~7th bit tempbyte = tempbyte << 1; // 6th tempbyte |= sda; if (position == 7) { // detect falling edge auxr0 &= ~int1h; _nop_ (); ie1 = 0; return; } else { ie1 = 0; return; } } else if (position == 8){ / / 9th bit - ack bit if (firstbyte) { if ((tempbyte >> 1) == twsi.addr) { sda = 0; } else { ex1 = 0; twsi.stage = i2c_disable; } } else { sda = 0; } } else { position = 0xff; // reset position auxr0 |= int1h; // reset scl interrupt for raising edge detection _nop_ (); ie1 = 0; sda = 1;
196 mg82fg5b xx data sheet megawin if (firstbyte) { firstbyte = 0; if ((tempbyte & 0x01) == 0x01) { twsi.slave_rw = 1; twsi.stage = i2c_sla_with_r; // for scl falling edge de tection auxr0 &= ~int1h; _nop_ (); ie1 = 0; } else { twsi.slave_rw = 0; twsi.stage = i2c_sla_with_w; } } else { twsi.stage = i2c_sl_w_ack; } twsi.iicbyte = tempbyte; twsi.completeabyte = 1; // set '1' when it tranfer a byte } } else { if (position < 7) { twsi.iicbyte = twsi.iicbyte << 1; // send 6~0th bit to sda sda = twsi.iicbyte & 0x80; } else if (position == 8) { twsi.completeabyte = 1; // set '1' when it tranfer a byte p osition = 0xff; // reset position if (sda) { twsi.stage = i2c_sl_r_nak; } else { twsi.stage = i2c_sl_r_ack; } return; } else { // ack/nak bit sda = 1; } } } ( 2 ). required function: s twi slave on sysclk=24mhz in burs t mode : assembly code example: $include (reg_mg8 2 f g 5 b32 .inc) slave_dev_addr equ 20h ; declare slave device address data_length equ 32 ; declare buffer size ; ------------------------------------------------------------------------- ; declare the twsi state ; ------------------------------------------------------------------------- i2c_slavestandby equ 0x00 i2c_sla_with_w equ 0x01 i2c_sla_with_r equ 0x02 i2c_disable equ 0x03 i2c_sl_w_ack equ 0x04 i2c_sl_r_ack equ 0x05 i2c_sl_r_nak eq u 0x06 ; ------------------------------------------------------------------------- ; declare the twsi pin ; -------------------------------------------------------------------------
megawin mg82fg5b xx data sheet 197 sda equ p3. 2 scl equ p3.3 ; -------------------------------------- ----------------------------------- ; data area ; ------------------------------------------------------------------------- controldata segment data rseg controldata receivestring: ds data_length ; data buffer stack: ds 40 ; stack area size positio n: ds 1 tempbyte: ds 1 addr: ds 1 iicbyte: ds 1 stage: ds 1 bitdata segment bit rseg bitdata firstbyte: dbit 1 ; the flag for receive sla+r/w completeabyte: dbit 1 ; set complete flag when transfer/receive one byte slave_rw: d bit 1 ; clear slave_rw to beceive / set to transfer disabletwsi: dbit 1 ; clear disabletwsi to active twsi transreceiver starttwsi: dbit 1 ; ------------------------------------------------------------------------- ; code area ; ----------------- -------------------------------------------------------- cseg at 0000h ;start address = 0x0000 jmp assembly_main cseg at 0013h ; ex0 interrupt isr address jmp scl_detect_isr cseg at 00 5 bh ; detect staf or stof isr address jmp systemf lag_isr twsi_cs segment code rseg twsi_cs using 0 assembly_main: mov sp,#stack ; initial sp for stack size anl ckcon0,#11111000b ; system clock / 1 call initial_twsi ; initial twsi main_loop: ; to do ... mov acc,stage xrl a,#i2c_d isable jz main_loop jnb completeabyte,main_loop ; have a event ? ; ------------------------------------------- mov acc,stage cjne a,#i2c_sla_with_w,subroutine_i2c_sla_with_r subroutine_i2c_sla_with_w: mov r1,#receivestring ; ini tial for receive clr completeabyte ; clear event flag jmp main_loop subroutine_i2c_sla_with_r: cjne a,#i2c_sla_with_r,subroutine_i2c_sl_w_ack
198 mg82fg5b xx data sheet megawin mov r1,#receivestring ; initial for transfer mov a,@r1 mov iicbyte,a rlc a ; it mu st transfer msb to sda mov sda,c clr completeabyte ; clear event flag jmp main_loop subroutine_i2c_sl_w_ack: cjne a,#i2c_sl_w_ack,subroutine_i2c_sl_r_ack mov @r1,iicbyte ; save data to "receivestring" inc r1 ; limit buff er index cjne r1,#receivestring+data_length,$+3+2 mov r1,#receivestring clr completeabyte ; clear event flag jmp main_loop subroutine_i2c_sl_r_ack: cjne a,#i2c_sl_r_ack,subroutine_i2c_sl_r_nak inc r1 ; limit buffer index cjne r1,#receivestring+data_length,$+3+2 mov r1,#receivestring mov iicbyte,@r1 ; prepare data form data buffer mov acc,@r1 rlc a mov sda,c ; sda = msb clr completeabyte ; clear event flag jmp main_loop subroutine_i2c_sl_r_nak : cjne a,#i2c_sl_r_nak,main_loop setb sda ; nak - event clr completeabyte jmp main_loop ; ------------------------------------------------------------------------- ; initial twsi interrupt (priority) & trigger mode ; ------------------------- ------------------------------------------------ initial_twsi: ; system flag have the highest priority orl eip1h,#08h orl eip1l,#08h ; the ex1 priority orl ip0h,#00000100b anl ip0l,#11111011b ; enable etwsi orl eie1,#esf orl sfie,#sdifie setb ea ; p33 & p3 2 is open drain mode for twsi mov p3m0,# 0c h mov p3m1,# 0c h ; edge detect setb it1 orl auxr0,#int1h
megawin mg82fg5b xx data sheet 199 ; declare slave device address mov addr,#slave_dev_addr mov stage,#i2c_disable clr completeabyte ret ; -------------- ----------------------------------------------------------- ; inital twsi's sda (staf & stof) edge detection ; ------------------------------------------------------------------------- systemflag_isr: push acc push psw mov acc, auxr1 ; check staf o r stof ? jb acc.3, staf_routine jb acc.2, stof_routine exit_flag_isr: pop psw pop acc reti staf_routine: ; start of twsi orl auxr0, #int1h ; initial ex0 for raising edge detection and enable ex0 interrupt nop clr ie1 setb sda setb ex1 clr disabletwsi ; clear disabletwsi flag to 0 (= active twsi) anl auxr1, #~staf ; clear staf flag clr slave_rw ; clear for receive a byte or address mov stage,#i2c_slavestandby setb firstbyte ; address byte flag setb starttwsi jmp exit_flag_isr stof_routine: ; stop of tswi clr ex1 ; disable ex0 interupt service routine anl auxr1,#~stof ; clear stof flag setb disabletwsi ; disable disabletwsi (= inactive twsi) mov stage,#i2c_disable j mp exit_flag_isr ; ------------------------------------------------------------------------- ; access sda by ex1 interrupt ; ------------------------------------------------------------------------- scl_detect_isr: push acc push psw jnb slave_rw, sl ave_write jmp slave_read ; -------------------------------------------------------------------------- slave_write: jnb starttwsi,$+5 clr starttwsi mov c, sda ; msb - bit 7 mov a, tempbyte ; left shift sda to tempbyte.0 rlc a mov tempb yte, a clr ie1 ; wait for ie1 jb ie1, $+6 jnb disabletwsi, $ - 3 ; avoid stof event
200 mg82fg5b xx data sheet megawin jnb starttwsi,$+6 ljmp exit_scl_detect_isr mov c, sda ; bit 6 mov a, tempbyte rlc a mov tempbyte, a clr ie1 jb ie1, $+6 jnb disabletwsi , $ -3 jnb starttwsi,$+6 ljmp exit_scl_detect_isr mov c, sda ; bit 5 mov a, tempbyte rlc a mov tempbyte, a clr ie1 jb ie1, $+6 jnb disabletwsi, $ -3 jnb starttwsi,$+6 ljmp exit_scl_detect_isr mov c, sda ; bit 4 mov a, temp byte rlc a mov tempbyte, a clr ie1 jb ie1, $+6 jnb disabletwsi, $ -3 jnb starttwsi,$+6 ljmp exit_scl_detect_isr mov c, sda ; bit 3 mov a, tempbyte rlc a mov tempbyte, a clr ie1 jb ie1, $+6 jnb disabletwsi, $ -3 jnb starttw si,$+6 ljmp exit_scl_detect_isr mov c, sda ; bit 2 mov a, tempbyte rlc a mov tempbyte, a clr ie1 jb ie1, $+6 jnb disabletwsi, $ -3 jnb starttwsi,$+6 ljmp exit_scl_detect_isr mov c, sda ; bit 1 mov a, tempbyte rlc a mov t empbyte, a clr ie1 jb ie1, $+6 jnb disabletwsi, $ -3 jnb starttwsi,$+6 ljmp exit_scl_detect_isr mov c, sda ; bit 0 mov a, tempbyte rlc a mov tempbyte, a clr ie1
megawin mg82fg5b xx data sheet 201 jb disabletwsi, exit_without_complete_flag jnb starttwsi,$+6 ljmp exit_scl_detect_isr anl auxr0, #~int1h ; set ex1 to falling edge detection nop clr ie1 jb ie1, $+6 jnb disabletwsi, $ -3 jnb firstbyte,slave_write_response_ack mov acc,tempbyte clr c rrc a cjne a,addr,not_slave_addr slave_writ e_response_ack: clr sda jmp complete_write_one_byte not_slave_addr: clr ex1 mov stage,#i2c_disable jmp exit_scl_detect_isr complete_write_one_byte: ; 9th falling edge clr ie1 jb ie1, $+6 ; wait for the 9th bit jnb disabletwsi , $ -3 setb sda ; set sda for input orl auxr0, #int1h ; set ex1 to edge detection nop clr ie1 setb completeabyte ; set '1' when it receives a byte jnb firstbyte,repeat_receive_mode clr firstbyte ; sla+w or sla+r ? clr sl ave_rw mov acc,tempbyte jnb acc.0,set_in_slaw_mode setb slave_rw anl auxr0,#~int1h ; the falling edge of ack signal nop clr ie1 mov stage,#i2c_sla_with_r jmp exit_scl_detect_isr set_in_slaw_mode: mov stage,#i2c_sla_with_w jmp ex it_scl_detect_isr repeat_receive_mode: mov iicbyte,tempbyte mov stage,#i2c_sl_w_ack ; -------------------------------------------------------------------------- exit_scl_detect_isr: pop psw pop acc reti
202 mg82fg5b xx data sheet megawin exit_without_complete_flag: clr compl eteabyte jmp exit_scl_detect_isr ; -------------------------------------------------------------------------- slave_read: ; must transfer tempbyte.7 in main routine ; and set ex1(scl) for falling edge detection jnb starttwsi,$+5 clr starttwsi m ov a,iicbyte ; transfer iicbyte.6 rl a mov iicbyte,a rlc a mov sda,c jnb starttwsi,$+6 ljmp exit_scl_detect_isr clr ie1 ; wait for ie1 jb ie1, $+6 jnb disabletwsi, $ -3 ; avoid stof event jnb starttwsi,$+6 ljmp exit_scl_detect_isr mov a,iicbyte ; transfer iicbyte.5 rl a mov iicbyte,a rlc a mov sda,c clr ie1 jb ie1, $+6 jnb disabletwsi, $ -3 jnb starttwsi,$+6 ljmp exit_scl_detect_isr mov a,iicbyte ; transfer iicbyte.4 rl a mo v iicbyte,a rlc a mov sda,c clr ie1 jb ie1, $+6 jnb disabletwsi, $ -3 jnb starttwsi,$+6 ljmp exit_scl_detect_isr mov a,iicbyte ; transfer iicbyte.3 rl a mov iicbyte,a rlc a mov sda,c clr ie1 jb ie1, $+6 jnb disabletwsi , $ -3 jnb starttwsi,$+6 ljmp exit_scl_detect_isr mov a,iicbyte ; transfer iicbyte.2 rl a mov iicbyte,a rlc a mov sda,c clr ie1 jb ie1, $+6 jnb disabletwsi, $ -3 jnb starttwsi,$+6 ljmp exit_scl_detect_isr
megawin mg82fg5b xx data sheet 203 mov a,iicbyte ; transfer iicbyte.1 rl a mov iicbyte,a rlc a mov sda,c clr ie1 jb ie1, $+6 jnb disabletwsi, $ -3 jnb starttwsi,$+6 ljmp exit_scl_detect_isr mov a,iicbyte ; transfer iicbyte.0 rl a mov iicbyte,a rlc a mov sda,c clr i e1 jb ie1, $+6 jnb disabletwsi, $ -3 jnb starttwsi,$+6 ljmp exit_scl_detect_isr setb sda ; for 9th bit - ack / nak clr ie1 jb ie1, $+6 jnb disabletwsi, $ -3 jnb sda,set_i2c_slave_read_ack mov stage,#i2c_sl_r_nak jmp complete_read _one_byte set_i2c_slave_read_ack: mov stage,#i2c_sl_r_ack complete_read_one_byte: clr ie1 setb completeabyte ; set '1' when it tranfer a byte jmp exit_scl_detect_isr ; --------------------------------------------------------------------- -------------- end c code example: #include #include #define slave_dev_addr 0x20 // declare slave device address #define data_length 32 // declare buffer size //---------------------------------- ------------------------------------------- // declare i2c stage // ----------------------------------------------------------------------------- #define i2c_slavestandby 0x00 #define i2c_sla_with_w 0x01 #define i2c_sla_with_r 0x02 #define i2c_disable 0x03 #define i2c_sl_w_ack 0x04 // sla_w with data ack #define i2c_sl_r_ack 0x05 // sla_r with data ack #define i2c_sl_r_nak 0x06 // sla_r with data nak // ----------------------------------------------------------------------------- // declare global variable // ----------------------------------------------------------------------------- typedef struct { unsigned char addr; unsigned char iicbyte; unsigned char stage:8;
204 mg82fg5b xx data sheet megawin unsigned char completeabyte:1; unsigned char sl ave_rw:1; } _twsi; _twsi twsi; unsigned char tempbyte; bit firstbyte,disabletwsi,starttwsi; // ----------------------------------------------------------------------------- // declare the twsi pin // ----------------------------------------------------------------------------- sbit sda = p3^ 2 ; sbit scl = p3^3; // ----------------------------------------------------------------------------- // initial twsi interrupt (priority) & trigger mode // ----------------------------------------------------------------------------- void initial_twsi () { // system flag have the highest priority eip1h |= 0x08; eip1l |= 0x08; // the ex1 have normal priority ip0h |= 0x08; ip0l &= ~0x08; eie1 |= esf; // enable etwsi sfie |= sdifie; ea = 1; // p33 & p 3 2 is open drain mode for twsi p3m0 = 0x 0c ; p3m1 = 0x 0c ; it1 = 1; auxr0 |= int1h; // declare slave device address twsi.addr = slave_dev_addr; twsi.completeabyte = 0; twsi.stage = i2c_disable; } // ----------------------------------------------------------------------------- // main() // ----------------------------------------------------------------------------- void main(void) { unsigned char bufferindex; unsigned char receivestring [data_length]; ckcon0 &= ~0x07; // system clock / 1 ini tial_twsi (); // initial interrupt and priority while (1) { if (twsi.stage != i2c_disable) { if (twsi.completeabyte == 1) { switch (twsi.stage) { case i2c_sla_with_w: bufferindex = 0; // initial bufferindex twsi.completeaby te = 0; twsi.stage = i2c_slavestandby; break; case i2c_sla_with_r: // prepare msb on sda pin twsi.iicbyte = receivestring [0];
megawin mg82fg5b xx data sheet 205 sda = twsi.iicbyte & 0x80; bufferindex = 0; // initial bufferindex twsi.completeab yte = 0; twsi.stage = i2c_slavestandby; break; case i2c_sl_w_ack: receivestring [bufferindex] = twsi.iicbyte; twsi.completeabyte = 0; bufferindex ++; // limit bufferindex 0~31 bufferindex &= 0x1f; twsi.stage = i2c_slavestandby; break; case i2c_sl_r_ack: bufferindex ++; // limit bufferindex 0~31 bufferindex &= 0x1f; twsi.iicbyte = receivestring [bufferindex]; sda = twsi.iicbyte & 0x80; twsi.completeabyte = 0; twsi. stage = i2c_slavestandby; break; case i2c_sl_r_nak: sda = 1; twsi.completeabyte = 0; twsi.stage = i2c_slavestandby; break; } } } // to do ... } } // ----------------------------------------------------------------------------- // inital twsi's sda (staf & stof) edge detection // ----------------------------------------------------------------------------- void systemflag_isr (void) interrupt 11 { unsigned char tempreg; tempreg = au xr1; auxr1 &= ~(staf+stof); // clear staf & stof flag if (tempreg & stof) { ex1 = 0; disabletwsi = 1; twsi.stage = i2c_disable; } else if (tempreg & staf){ auxr0 |= int1h; _nop_ (); ie1 = 0; sda = 1; ex1 = 1; disabletwsi = 0; // avoid mistake twsi.slave_rw = 0; // clear for receive a byte or address
206 mg82fg5b xx data sheet megawin twsi.stage = i2c_slavestandby; firstbyte = 1; starttwsi = 1; } } // ------------------------------------------------------------------------- // access sda by ex1 interrupt // ------------------------------------------------------------------------- void twsi_ex1_isr(void) interrupt 2 { if (twsi.slave_rw == 0) { if (starttwsi) { starttwsi = 0; } tempbyte = tempbyte << 1; // bit 7 tempbyte |= sda; ie1 = 0; while ((ie1 | disabletwsi) == 0); // bit 6 if (starttwsi) return; tempbyte = tempbyte << 1; tempbyte |= sda; ie1 = 0; while ((ie1 | disabletwsi) == 0); if (starttwsi) return; tempbyte = tempbyte << 1; // bi t 5 tempbyte |= sda; ie1 = 0; while ((ie1 | disabletwsi) == 0); if (starttwsi) return; tempbyte = tempbyte << 1; // bit 4 tempbyte |= sda; ie1 = 0; while ((ie1 | disabletwsi) == 0) ; if (starttwsi) return; tempbyte = tempbyte << 1; // bit 3 tempbyte |= sda; ie1 = 0; while ((ie1 | disabletwsi) == 0); if (starttwsi) return; tempbyte = tempbyte << 1; // bit 2 tempbyte |= sda; ie1 = 0; while ((ie1 | disabletwsi) == 0); if (starttwsi) return; tempbyte = tempbyte << 1; // bit 1 tempbyte |= sda; ie1 = 0; while ((ie1 | disabletwsi) == 0); if (starttwsi) return; tempbyte = tempbyte << 1; // bit 0 tempbyte |= sda; auxr0 &= ~int1h; // for scl edge detection _nop_ (); ie 1 = 0; while ((ie1 | disabletwsi) == 0); // 0th falling edge if (starttwsi) return;
megawin mg82fg5b xx data sheet 207 if (disabletwsi) return; if (firstbyte) { if ((tempbyte >> 1) == slave_dev_addr) { sda = 0; } else { ex1 = 0; twsi.stage = i2c_disable; } } else { sda = 0; } ie1 = 0; while ((ie1 | disabletwsi) == 0); sda = 1; auxr0 |= int1h; // for scl raising edge detection _nop_ (); ie1 = 0; if (firstbyte) { firstbyte = 0; twsi.slave_rw = (tempbyte & 0x01); if (tempbyte & 0x01) { twsi.slave_rw = 1; twsi.stage = i2c_sla_with_r; // for scl falling edge detection auxr0 &= ~int1h; _nop_ (); ie1 = 0; } else { twsi.slave_rw = 0; twsi.stage = i2c_sla_with_w; } } else { twsi.stage = i2c_sl_w_ack; } twsi.iicbyte = tempbyte; if (disabletwsi) return; twsi.completeabyt e = 1; // set '1' when it tranfer a byte p35 = 1; } else { if (starttwsi) { starttwsi = 0; } twsi.iicbyte = twsi.iicbyte << 1; sda = twsi.iicbyte & 0x80; // bit 6 ie1 = 0; while ((ie1 | disabletwsi) == 0); if (starttwsi) return; twsi.iicbyte = twsi.iicbyte << 1; sda = twsi.iicbyte & 0x80; // bit 5 ie1 = 0; while ((ie1 | disabletwsi) == 0); if (starttw si) return; twsi.iicbyte = twsi.iicbyte << 1; sda = twsi.iicbyte & 0x80; // bit 4 ie1 = 0; while ((ie1 | disabletwsi) == 0);
208 mg82fg5b xx data sheet megawin if (starttwsi) return; twsi.iicbyte = twsi.iicbyte << 1; sda = twsi.iicbyte & 0x80; // bit 3 ie1 = 0; while ((ie1 | disabletwsi) == 0); if (starttwsi) return; twsi.iicbyte = twsi.iicbyte << 1; sda = twsi.iicbyte & 0x80; // bit 2 ie1 = 0; while ((ie1 | disabletwsi) == 0); if (starttwsi) return; twsi.iicbyte = twsi.iicbyte << 1; sda = twsi.iicbyte & 0x80; // bit 1 ie1 = 0; while ((ie1 | disabletwsi) == 0); if (starttwsi) return; twsi.iicbyte = twsi.iicbyte << 1; sda = twsi.iicbyte & 0x80; // bit 0 ie1 = 0; while ((ie1 | disabletwsi) == 0); sda = 1; // ack ie1 = 0; while ((ie1 | disabletwsi) == 0); ie1 = 0; if (disabletwsi) return; if (sda) { twsi.stage = i2c_sl_r_nak; } else { twsi.stage = i2c_sl_r_ack; } twsi.completeabyte = 1; } }
megawin mg82fg5b xx data sheet 209 23. be eper the beeper function outputs a signal on the beep pin for sound generation. the signal is in the range about 1, 2 or 4 khz which is divided from ilrco. figure 23? 1 shows the beeper generator circuit. but ilrco is not the precision clock source. please refer section ? 31.5 ilrco characteristics ? for more detailed ilrco frequency deviation range. figure 23? 1 . beeper generator beep ilrco ( 32khz) 16 8 32 0 1 2 3 bpoc[1:0] (auxr3.5~4) 00: p4.4 01: ilrco/32 (~= 1k) 10: ilrco/16 (~= 2k) 11: ilrco/8 (~= 4k) sfr p4.4 23.1. beeper register auxr3: auxiliary register 3 sfr page = 0~f sfr address = 0xa4 reset = 0000 - 0000 7 6 5 4 3 2 1 0 staf stof bpoc1 bpoc0 gf p1s0mi p3eci p3twi1 r/w r/w r/w r/w r/w r/w r/w r/w bit 5~4 : bpoc1~0 , be eper output control bits. bpoc[1:0] p4.4 function i/o mode 00 p 4 . 4 b y p4m0.4 01 ilrco/64 b y p4m0.4 10 ilrco/32 b y p4m0.4 11 ilrco/16 b y p4m0.4 for beeper on p 4 . 4 function, it is recommended to set p 4 m0. 4 to ? 1 ? which selects p 4 . 4 as push - push output m ode.
210 mg82fg5b xx data sheet megawin 23.2. beeper sample code (1). required function: set beeper output 1khz assembly code example: orl p 4 m0,# 1 0h ; set p 4 . 4 to push - pull output mode anl auxr1,#~(bpoc1|bpoc0) ; set p4 . 4 as gpio function orl auxr1,#bpoc0 ; beep = ilrco/64 ~= 1khz c code example: p1m0 = p 4 m0 | 0x 1 0; // set p 4 . 4 to push - pull output mode auxr1 &= ~(bpoc1 | bpoc0); // set p4 . 4 as gpio function auxr1 |= bpoc0; // beep = ilrco/64 ~= 1khz
megawin mg82fg5b xx data sheet 211 24. keypad interrupt (kbi) the keypad interrupt function is intended primarily to allow a single interrupt to be generated when port 2 is equal to or not equal to a certain pattern. this function can be used for bus address recognition or keypad recognition. there are three sfrs used for this function. the keypad interrupt mask register (kbmask) is used to define which input pins connected to port 2 are enabled to trigger the interrupt. the keypad patter n register (kbpatn) is used to define a pattern that i s compared to the value of keypad input . the keypad interrupt flag (kbif) in the keypad interrupt control register (kbcon) is set by hardware when the condition is matched. an interrupt will be generate d if it has been enabled by setting the ekbi bit in e ie 1 register and ea=1. the patn_sel bit in the keypad interrupt control register (kbcon) is used to define ?equal? or ?not - equal? for the comparison. the keypad input can be selected from the port pins o n port 1 and port 3 by p1kbih and p3kbil, auxr1.7~6. the default keypad input is indexed on port 2. in order to use the keypad interrupt as the ?keyboard? interrupt, the user needs to set kbpatn=0xff and patn_sel=0 (not equal), then any key connected to k eypad input which is enabled by kbmask register will cause the hardware to set the interrupt flag kbif and generate an interrupt if it has been enabled. the interrupt may wake up the cpu from idle mode or power - down mode. this feature is particularly usefu l in handheld, battery powered systems that need to carefully manage power consumption but also need to be convenient to use. 24.1. keypad register the following special function registers are related to the kbi operation: kbpatn: keypad pattern register sfr page = 0~f sfr address = 0xd5 reset= 1111 - 1111 7 6 5 4 3 2 1 0 kbpatn.7 kbpatn.6 kbpatn.5 kbpatn.4 kbpatn.3 kbpatn.2 kbpatn.1 kbpatn.0 r /w r /w r /w r/w r /w r /w r/w r/w bit 7~0: kbpatn.7~0: the keypad pattern, reset value is 0xff. kbcon: keypad cont rol register sfr page = 0~f sfr ad dress = 0xd6 reset= xxxx - xx01 7 6 5 4 3 2 1 0 -- -- -- -- -- -- patn_sel kbif w w w w w w r/w r/w bit 7~2: reserved. software must write ? 0 ? on these bits when kbcon is written. bit 1: patn_sel , pattern matching po larity selection. 0: the keypad input has to be not equal to user - defined keypad pattern in kbpatn to generate the interrupt. 1: the keypad input has to be equal to the user - defined keypad pattern in kbpatn to generate the interrupt. bit 0: kbif , keypad i nterrupt flag. the default value of kbif is set to ? 1 ? . 0: must be cleared by software by writing ?0?. 1: set when keypad input matches user defined conditions specified in kbpatn, kbmask, and patn_sel.
212 mg82fg5b xx data sheet megawin kbmask: keypad interrupt mask register sfr page = 0~f sfr address = 0xd7 reset= 0000 - 0000 7 6 5 4 3 2 1 0 kbmask.7 kbmask.6 kbmask.5 kbmask.4 kbmask.3 kbmask.2 kbmask.1 kbmask.0 r /w r /w r /w r/w r /w r /w r/w r/w kbmask.7: when set, enables kbi7 as a cause of a keypad interrupt on p2.6 or p1.3 which is selected by p1kbih (auxr1.7) setting. kbmask.6: when set, enables kbi 6 as a cause of a keypad interrupt on p2. 4 or p1. 2 which is selected by p1kbih (auxr1. 7 ) setting. kbmask.5: when set, enables kbi 5 as a cause of a keypad interrupt on p2. 3 or p1. 1 whic h is selected by p1kbih (auxr1. 7 ) setting. kbmask.4: when set, enables kbi 4 as a cause of a keypad interrupt on p2. 2 or p1. 0 which is selected by p1kbih (auxr1. 7 ) setting. kbmask.3: when set, enables kbi 3 as a cause of a keypad interrupt on p2. 7 or p 3 . 5 wh ich is selected by p 3 kbi l (auxr1. 6 ) setting. kbmask.2: when set, enables kbi 2 as a cause of a keypad interrupt on p2. 5 or p 3 . 4 which is selected by p 3 kbi l (auxr1. 6 ) setting. kbmask.1: when set, enables kbi 1 as a cause of a keypad interrupt on p2. 1 or p 3 . 1 which is selected by p 3 kbi l (auxr1. 6 ) setting. kbmask.0: when set, enables kbi 0 as a cause of a keypad interrupt on p2. 0 or p 3 . 0 which is selected by p 3 kbi l (auxr1. 6 ) setting. auxr1 : auxiliary control register 1 sfr page = 0~f sfr address = 0xa2 r eset = 0000 - 0000 7 6 5 4 3 2 1 0 p1kbih p3kbil p4spi p3s1 p3s1mi p6twi p3cex dps r/w r/w r/w r/w r /w r /w r /w r/w bit 7: p1kbih, kbi high nibble port selection on p1.3, p1.2, p1.1 and p1.0. p1kbih kbi.7~4 0 p2.6, p2.4, p2.3, p2.2 1 p1.3, p1.2, p1.1, p1.0 bit 6: p3kbil, kbi low nibble port selection on p3.5, p3.4, p3.1 and p3.0. p3kbil kbi.3~0 0 p2.7, p2.5, p2.1, p2.0 1 p3.5, p3.4, p3.1, p3.0
megawin mg82fg5b xx data sheet 213 24.2. keypad interrupt sample code (1). required function: implement a kbi function on p 2 assembly code example: org 0003bh kbi_int: mov kbcon, #00h ;clear kp interrupt flag mov kbmask, #00h ;will disable kp interrupt reti main: mov pucon0, # 3 fh ;enable p0, p1 p2 internal pull high orl eie1, #20h setb ea delay_ms 5 mov kbpatn, #0ffh m ov kbcon, #00h mov kbmask, #0ffh ;will enable kp interrupt clr p1.0 orl pcon0, #02h ;into power down clr p1.1 ;pull low any p0.x will wake up mcu. loop: jmp loop c code example: void kbi _isr(void) interrupt 7 { kbcon=0; kbma sk=0; } void main(void) { pucon0 = 0x3f; // enable p 0 ~p 2 on - chip pull - up resistor eie1 |= ekb ; // enable kbi interrupt ea = 1; // enable global interrupt delay_5ms(); kbpatn=0xff; kbcon=0; kbmask=0xff; p10=0; pcon0 |= pd; // set mcu into power - down mode p11=0; while(1); }
214 mg82fg5b xx data sheet megawin 25. 10 - bit adc the adc subsystem for the mg82fg5bxx consists of an ana log multiplexer (amux), a nd a 2 00 ksps , 1 0 - bi t successive - approximation - register adc. the amux can be configured via the special function registers shown in figure 25? 1 . adc operates in single - ended mode, and may b e configured to measure any of the pins on port 1 or internal reference . the adc subsystem is enabled only when the ad c en bit in the adc control register ( adc o n 0 ) is set to logic 1. the adc subsystem is in low power shutdown when this bit is logic 0. 25.1. adc structure figure 25? 1 . adc block diagram amux (p1.0) ain0 (p1.1) ain1 (p1.2) ain2 (p1.3) ain3 (p1.4) ain4 (p1.5) ain5 (p1.6) ain6 (p1.7) ain7 10-bit adc b9 b8 b7 b6 b5 b4 b3 b2 -- -- -- -- b1 b0 adcdh adcdl adcen -- ch3 adci adcs ch2 ch1 ch0 adcon0 /2 /4 /8 /16 /32 /64 sysclk adc clock, 6mhz (max.) 10 load adcks2 adcks1 adcks0 adrj adps vrs0 adtm1 adtm0 t0of ain adcfg0 t0of/2 s1tof/2 s1tof -- -- sign + aos.3~0 offset cancellation -- vrs2 vrs1 sign aos.3 aos.2 aos.1 aos.0 adcfg1 (2.4v) int. vref vref+ vdd int. vref 2.4v ext. vref vrs2~0
megawin mg82fg5b xx data sheet 215 25.2. adc operation adc has a maximum conversion speed of 2 0 0 ksps. the adc conversion clock is a divided version of the system clock or the timer overflow rate o f s1brg and timer 0 , determined by the ad ck s2~0 bits in the adc fg0 re gister . the adc conversion clock should be no more than 6 mhz. after the conversion is complete (ad c i is high), the conversion result can be found in the adc result registers (adc dh , adc dl ). for single ended conversion, the result is adc result = vdd voltage v in ? x 1024 25.2.1. adc input channels the analog multiplexer (amux) selects the inputs to the adc, allowing any of the pins on port 1 to be measured in single - ended mode. the adc input chan nels are configured and selected by chs 3 ~0 in the adcon 0 register as described in figure 25 ? 1 . the selected pin is measured with respect to gnd. 25.2.2. starting a conversion prior to using the adc function, the user should: 1) turn on the adc hardwa re by setting the ad cen bit, 2) select adcms to configure adc for single - ended mode or fully - differential mode 3 ) configure the adc input clock by bits a d cks2, adcks 1 and adcks 0, 4 ) select the analog input channel by bits chs3, chs2, chs1 and chs0, 5) configure the adc voltage reference source 6 ) configure the selected input (shared with p1) to the analog - input - only mode by p1, p1m0 and p1 aio registers, and 7 ) configure adc result arrangement using adrj bit. now, user can set the adcs bit to start th e a - to - d conversion. the conversion time is controlled by bits adcks2, adcks1 and adcks 0. once the conversion is completed, the hardware will automatically clear the adcs bit, set the interrupt flag adci and load the 1 0 bits of conversion result into adch and adcl (according to adrj bit) simultaneously. if user sets the adcs and selects the adc trigger mode to s1brg / timer0 o ver flow or free - run, then the adc will keep conversion continuously unless adcen is cleared or configure adc to manual mode. as descr ibed above, the interrupt flag adci, when set by hardware, shows a completed conversion. thus two ways may be used to check if the conversion is completed: (1) always polling the interrupt flag adci by software; (2) enable the adc interrupt by setting bits eadc (in e ie 1 register) and ea (in ie register), and then the cpu will jump into its interrupt service routine when the conversion is completed. regardless of (1) or (2), the adci flag should be cleared by software before next conversion. 25.2.3. adc conversion time the user can select the appropriate conversion speed according to the frequency of the analog input signal. the maximum input clock of the adc is 6mhz and it operates a fixed conversion time with 30 adc clocks. user can configure the adcks2~0 in adc fg0 to specify the conversion rate. for example, if sysclk = 1 2mhz and the adcks = sysclk/2 is selected, then the frequency of the analog input should be no more than 2 00 khz to maintain the conversion accuracy. (conversion rate = 12mhz /2/ 30 = 2 00 khz. ) 25.2.4. i/o pins used with adc function the analog input pins used for the a/d converters also have its i/o port ?s digital input and output function. in order to give the proper analog performance, a pin that is being used with the adc should ha ve its digital output as disabled. it is done by putting the port pin into the input - only mode. and w hen an analog signal is applied to
216 mg82fg5b xx data sheet megawin the adc i7~ 0 pin and the digital input from this pin is not needed, software could set the corresponding pin to analog - input - only in p1aio to reduce power consumption in the digital input buffer. the port pin configuration for analog input function is described in the section ? 14.2.1 port 1 register ? . 25.2.5. idle a nd power - down mode if the ad c is turned on i n idle mode and power - down mode, it will consume a little power. so, power consumption can be reduced by turning off the adc hardware (ad ce n=0) before entering idle mode and power - down mode. in power - down mode, the adc does not function. if software triggers the adc operation in idle mode, the adc will finish the conversion and set the adc interrupt flag, adci. when the adc interrupt enable (eadc, eie1.1) is set, the adc interrupt will wake up cpu from idle mode .
megawin mg82fg5b xx data sheet 217 25.3. adc register a d c on0 : a dc control register 0 sfr page = 0~f sfr address = 0xc4 reset = 00 0 0 - 0000 7 6 5 4 3 2 1 0 ad cen -- chs3 a dci a dcs c hs 2 c hs 1 c hs 0 r/w w r/ w r/w r/w r/w r/w r/w bit 7: adcen , adc enable . 0: clear to turn off the adc block. 1: set to turn on the adc block. at least 5us adc enabled time is required before set adcs. bit 6: reserved. software must write ? 0 ? on this bit when adcon0 is written. bit 5: chs3 . combined ch2~0 to select adc input channel. bit 4: a d c i, adc interrupt flag. 0: the flag must be cleared by software. 1: this flag is set when an a/d conversion is completed. an interrupt is invoked if it is enabled. bit 3: a d c s . a dc start of conversion . 0: adcs cannot be cleared by software. 1: setting this bit by software starts an a/d conversion. on completion of the conversion, the adc hardware will clear adcs and set the adci. a new conversion may not be started while either adcs or adci is high. bit 2~0: chs 2 ~ c hs 1, input channel selection for adc analog multiplexer . in single - ended mode: chs 3~ 0 selected channel 0 0 0 0 ain0 (p1.0) 0 0 0 1 ain1 (p1.1) 0 0 1 0 ain2 (p1.2) 0 0 1 1 ain3 (p1.3) 0 1 0 0 ain4 (p1.4) 0 1 0 1 ain5 (p1.5) 0 1 1 0 ain6 (p1.6) 0 1 1 1 ain7 (p1.7) 1 0 0 0 res erved 1 0 0 1 reserved 1 0 1 0 reserved 1 0 1 1 reserved 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 gnda 1 1 1 1 int. vref (2.4v) a d c fg0 : a dc con figuration register 0 sfr page = 0~f sfr address = 0xc3 reset = 00 0 0 - 00 00 7 6 5 4 3 2 1 0 adcks2 adcks1 adcks0 a drj adps vrs0 adtm 1 adtm 0 r/w r/w r/w r/w r/ w r/ w r/w r/w bit 7 ~5 : adc conversion clock select bits . adcks [ 1 :0] adc clock selection 0 0 0 sysclk/2 0 0 1 sysclk/4
218 mg82fg5b xx data sheet megawin 0 1 0 sysclk/8 0 1 1 sysclk/16 1 0 0 sysc lk/32 1 0 1 sysclk/64 1 1 0 s1tof/2 1 1 1 t0 of/2 note: 1. sysclk is the system clock . 2. s1tof is uart1 baud - rate generator overflow. 3. t0of is timer 0 overflow. bit 4: adrj, adc result right - justified selection. 0: the most significant 8 bits of conver sion result are saved in adch[7:0], while the least significant 2 bits in adcl[ 7 : 6 ]. 1: the most significant 2 bits of conversion result are saved in adch[ 1 :0], while the least significant 8 bits in adcl[7:0]. if adrj = 0 adcdh: adc date high byte registe r sfr page = 0~f sfr address = 0xc6 reset = xxxx - xxxx 7 6 5 4 3 2 1 0 (b9) (b8) (b7) (b6) (b5) (b4) (b 3 ) (b 2 ) r r r r r r r r adcl: adc data low byte register sfr page = 0~f sfr address = 0xc5 reset = xxxx - xxxx 7 6 5 4 3 2 1 0 (b1) (b0) -- -- - - -- -- -- r r r r r r r r if adrj = 1 adcdh 7 6 5 4 3 2 1 0 -- -- -- -- -- -- (b9) (b8) r r r r r r r r adcdl 7 6 5 4 3 2 1 0 (b7) (b6) (b5) (b4) (b3) (b2) (b1) (b0) r r r r r r r r when in single - ended mode, conversion codes are represented as 1 0 - bit unsigned integers. inputs are measured from ?0? to vref x 1023 / 1024 . example codes are shown below for both right - justified and left - justified data. unused bits in the adc d h and adc d l registers are set to ?0?. input voltage (single - ended) adcdh:ad cdl (adrj = 0) adcdh:adcdl (adrj = 1) vref+ x 1023/1024 0xff c 0 0x0 3 ff vref + x 512 / 1024 0x8000 0x0 2 00 vref + x 256/1024 0x4000 0x0 1 00 vref + x 128/1024 0x2000 0x0 08 0 0 0x0000 0x0000 bit 3: adps. reserved for test mode. software must write 0. bit 2: vr s0. combined vrs2 and vrs1 configure the source of adc voltage reference (vref+).
megawin mg82fg5b xx data sheet 219 bit 1~ 0 : adc trigger mode selection. adtm [ 1 :0] adc conversion start selection 0 0 set adcs 0 1 timer 0 overflow 1 0 free running mode 1 1 s1 brg overflow adcfg 1: adc configuration register 1 sfr page = 0~f sfr address = 0xbb reset = x xx0 - 0000 7 6 5 4 3 2 1 0 -- vrs2 vrs1 sign aos.3 aos.2 aos.1 aos.0 r/ w r/ w r/ w r/w r/w r/w r/w r/w bit 7: reserved. software must write ? 0 ? on this bit when adcfg1 is written . bit 6~5: vrs2~vrs1. adc voltage reference selection control ( vrs2 , vrs1 and vrs0 ) . vrs[2:0] function s3, s2, s1 ldo_24_en 0 0 0 adc vref+ = vdda 0 1 0 dis 0 0 1 adc vref+ = ain1 external vref input 1 0 0 dis 0 1 0 adc vref+ = vdda, ldo24 f or ain15 0 1 0 en 0 1 1 adc vref+ = ldo_24 with ext. pad 1 0 1 en 1 0 0 adc vref+ = vdda 0 1 0 dis 1 0 1 adc vref+ = vdda 0 1 0 dis 1 1 0 adc vref+ = vdda with ext. pad 1 1 0 dis 1 1 1 adc vref+ = ldo_24 0 0 1 en ldo_24 int. vdda ext. pad (p1.1, ain1) s1 s2 s3 adc vref+ ldo_24_en bit 4~0: s ign and aos.3~0. the register value adjusts the adc result in {adch, adcl} for offset cancellation. {sign, aos.[3:0]} value in {adcdh, adcdl} 0_1111 adc transfer value + 15 0_1110 adc transfer value + 14 ?? ?? 0_0010 adc transfer value + 2 0_0001 adc transfer value + 1 0_0000 adc transfer value + 0 1_1111 adc transfer value ? 1 1_1110 adc transfer value ? 2 ?? ?? 1_0001 adc transfer value ? 15 1_0000 adc transfer value ? 16 p1aio: port 1 analog input only sfr page = 0~f sfr address = 0x92 r eset = 0000 - 0000 7 6 5 4 3 2 1 0 p17aio p16aio p15aio p14aio p13aio p12aio p11aio p10aio
220 mg82fg5b xx data sheet megawin r/w r/w r/w r/w r/w r/w r/w r/w 0: port pin has digital and analog input capability. 1: port pin only has analog input only. the corresponding port pin register bi t will always read as zero when this bit is set.
megawin mg82fg5b xx data sheet 221 25.4. adc sample code
222 mg82fg5b xx data sheet megawin 26. isp and iap the f lash memory of mg82fg5bxx is partitioned into ap - memory, iap - memory and isp - memory. ap - memory is used to store user ? s application program; iap - memory is used to store the non - volatile application data; and, isp - memory is used to store the boot loader program for in - system programming. when mcu is running in isp region, mcu could modify the ap and iap memory for software upgraded. if mcu is running in ap region, softwar e could only modify the iap memory for storage data updated. 26.1. mg82fg5b32 flash memory configuration there are total 64 k bytes of flash memory in mg82fg5b32 and figure 26 ? 1 shows the device f lash configuration of m g82fg5b32 . the isp - memory can be configured as disabled or up to 4k bytes space by hardware option. the flash size of iap memory is located between the iap low boundary and iap high boundary. the iap low boundary is defined by the value of iaplb register. the iap high boundary is associated with isp start address which decides isp memory size by hardware option. the iaplb register value is configured by hardware option or ap software programming. all of the ap, iap and isp memory are shared the total 64k by tes flash memory. figure 26? 1 . mg82fg5b32 flash memory configuration 0x7000 if isp size = 4kb 0x7200 if isp size = 3.5kb 0x7400 if isp size = 3kb 0x7600 if isp size = 2.5kb 0x7800 if isp size = 2kb 0x7a00 if isp size = 1.5kb 0x7c00 if isp size = 1kb (1) isp start address: note: ap-memory isp-memory iap-memory 0x0000 0x7fff iap high boundary isp start address iap low boundary flash memory total: 32kb application code iap data isp code iaplb = 0x76 (default) iap start 0x7600 isp start 0x7a00 (default) (4) if isp is disabled: iap high boundary = 0x7fff iap low boundary = 0x7fff C iap size + 1 (3) if isp is enabled: iap high boundary = isp start address C 1 iap low boundary = isp start address C iap size (2) iap size : iaplb = iap low boundary (rom high-byte address) iap start address = { iaplb, 00h } iap size = isp start address C iap start address set laplb = change iap size note: in default, the mg82fg5b32 that megawin shipp ed had configured the flash memory for 1.5 k isp, 1 k i ap and lock enabled . the 1.5 k isp region is inserted megawin proprietary combo isp code to perform in - system - programming through megawin 1 - line isp protocol and com port isp. the 1 k iap size can be re - configured by software for application required.
megawin mg82fg5b xx data sheet 223 26.2. mg8 2fg5b xx flash access in isp/iap there are 3 flash access modes are provided in mg82fg5bxx for isp and iap application: page erase mode, program mode and read mode. mcu software uses these three modes to update new data into flash storage and get flash con tent. this section shows the flow chart and demo code for the various flash modes . before perform isp /iap operation, the user should fill the bits xcks 5 ~xcks0 in ckcon 1 register with a proper val ue. (refer to section ? 9.2 clock register ? ) to do page erase ( 512 bytes per page) step 1: set ms [2: 0]=[ 0, 1,1] in ispcr register to select page erase mode. step 2 : fill page address in ifadrh & ifadrl registers. step 3 : sequent ially write 0x46 h then 0xb9 h to scmd register to trigger an isp processing. to do byte program step 1: set ms [2: 0]=[ 0, 1,0] in ispcr register to select byte program mode. step 2 : fill byte address in ifadrh & ifadrl registers. step 3 : fill data to be prog rammed in ifd register. step 4 : sequentially write 0x46 h then 0xb9 h to scmd register to trigger an isp processing. to do read step 1: set ms [2: 0]=[ 0, 0,1] in ispcr register to select read mode. step 2: fill byte address in ifadrh & ifadrl registers. step 3: sequentially write 0x46 h then 0xb9 h to scmd register to trigger an isp processing. step 4: now, the flash data is in ifd register. the detailed descriptions of flash page erase, byte program and flash read in mg82fg5bxx is listed in the following secti ons:
224 mg82fg5b xx data sheet megawin 26.2.1. isp/iap flash page erase mode the any bit in flash data of mg82fg5bxx only can be programmed to ? 0 ? . if user would like to write a ? 1 ? into flash data, the flash erase is necessary. but the flash erase in mg82fg5bxx isp/iap operation only support ? page erase ? mode, a page erase will write all data bits to ? 1 ? in one page. there are 512 bytes in one page of mg82fg5bxx and the page start address is aligned to a8~a0 = 0x000. the targeted flash address is defined in ifadrh and ifadrl. so, in flash pag e erase mode, the ifadrh.0(a8) and ifadrl.7~0(a7~a0) must be written to ? 0 ? for right page address selection. figure 26 ? 2 shows the flash page erase flow in isp/iap operation. figure 26? 2 . isp/iap page erase flow define isp / iap time base enable isp/iap engine define targeted flash page address trigger engine for "erase" set "page erase" mode end of page no yes set standby and disable engine ==> configure ckcon1.xcks5~0 ==> set ispcr.ispen = "1" ==> define ifadrh & ifadrl ==> write ifmt.ms2~0 = "000" ==> set ispcr.ispen = "1" ==> write ifmt.ms2~0 = "011" ==> write scmd = 0x46, then ==> write scmd = 0xb9 start end
megawin mg82fg5b xx data sheet 225 figure 26? 3 shows the demo code of the isp/iap page erase operation. figure 26? 3 . demo code for isp/iap pag e erase mov ckcon1 ,# 0 0 0 0 1 011b ; xcks5~0 = decimal 11 when oscin = 12 mhz mov ispcr,#100000 00 b ; ispcr.7 = 1, enable isp mov ifmt,#03h ; select page erase mode mov ifadrh,?? ; fill [ifadrh,ifadrl] with page address mov ifadrl,?? ; mov scmd,#46h ; trigger isp /iap processing mov scmd,#0b9h ; ;now, mcu will halt here until processing completed mov ifmt,#0 0 h ; select standby mode mov ispcr,# 0 00000 00 b ; i spcr.7 = 0 , disab le isp
226 mg82fg5b xx data sheet megawin 26.2.2. isp/iap flash program mode the ? program ? mode of mg82fg5bxx provides the byte write operation into flash memory for new data updated. the ifadrh and ifadrl point to the physical flash byte address. ifd stores the content which will be programmed into the flash. figure 26? 4 shows the flash byte program flow in isp/iap operation. figure 26? 4 . isp/iap byte program flow define isp/iap time base enable isp/iap engine define targeted flash byte address trigger engine for "program" set byte "program" mode end of address no yes set standby and disable engine ==> configure ckcon1.xcks5~0 ==> set ispcr.ispen = "1" ==> define ifadrh & ifadrl ==> write ifmt.ms2~0 = "000" ==> set ispcr.ispen = "1" ==> write ifmt.ms2~0 = "010" ==> write scmd = 0x46, then ==> write scmd = 0xb9 ready for new stored data ==> write updated data to ifd start end
megawin mg82fg5b xx data sheet 227 figure 26? 5 shows the demo code of the isp/iap byte program operation. figure 26? 5 . demo code for isp/iap byte program mov ckcon1 ,# 0 000 1 011b ; xcks5~0 = decimal 11 when osc in = 12 mhz mov ispcr,#100000 00 b ; ispcr.7=1, enable isp mov ifmt,#02h ; select program mode mov ifadrh,?? ; fill [ifadrh,ifadrl] with byte address mov ifadrl,?? ; mov ifd,?? ; fill ifd with the data to be programmed mov scmd,#46h ; trigger isp /iap processing mov scmd,#0b9h ; ;now, mcu will halt here until processing completed mov ifmt,#0 0 h ; select standby mode mov ispcr,# 0 00000 00 b ; ispcr. 7 = 0 , disab le isp
228 mg82fg5b xx data sheet megawin 26.2.3. isp/iap flash read mode the ? read ? mode of mg82fg5bxx provides the byte read operation from flash memory to get the stored data. the ifadrh and ifadrl point to the physical flash byte address. ifd stores the data which is read from the flash content. it is recommended to verify the flash data by read mode after data programmed or page erase. figure 26? 6 shows the flash byte read flow in isp/iap operation. figure 26? 6 . isp/iap byte read flow define isp / iap time base enable isp/iap engine define targeted flash byte address trigger engine for "read" set byte "read" mode end of address no yes set standby and disable engine ==> configure ckcon1.xcks5~0 ==> set ispcr.ispen = "1" ==> define ifadrh & ifadrl ==> write ifmt.ms2~0 = "000" ==> set ispcr.ispen = "1" ==> write ifmt.ms2~0 = "001" ==> write scmd = 0x46, then ==> write scmd = 0xb9 get data ==> read stored data from ifd start end
megawin mg82fg5b xx data sheet 229 figure 26? 7 shows the demo code of the isp/iap byte read operation. figure 26? 7 . demo code for isp/iap byte read mov ckcon1 ,# 0 000 1 011b ; xcks5~0 = decimal 11 when oscin = 12 mhz mov ispcr,#100000 00 b ; ispcr.7=1, enable isp mov ifmt,#01h ; select read mode mov ifadrh,?? ; fill [ifadrh,ifadrl] with byte address mov i fadrl,?? ; mov scmd,#46h ; trigger isp /iap processing mov scmd,#0b9h ; ;now, mcu will halt here until processing completed mov a,ifd ; now, the read data exists in ifd mov ifmt,#0 0 h ; select standby mode mov ispcr,# 0 00000 00 b ; ispcr.7 = 0 , disab le isp
230 mg82fg5b xx data sheet megawin 26.3. isp operation isp means in - system - programming which makes it possible to update the user?s application program (in ap - memory) and non - volatile application data (in iap - me mory) without removing the mcu chip from the actual end product. this useful capability makes a wide range of field - update applications possible. the isp mode is used in the loader program to program both the ap - memory and iap - memory. note: (1) before us ing the isp feature, the user should configure an isp - memory space and pre - program the isp code ( boot loader program) into the isp - memory by a universal writer / programmer or megawin proprietary writer /programmer . (2) isp code in the isp - memory can only pro gram the ap - memory and iap - memory. after isp operation has been finished, software writes ? 001? on ispcr.7 ~ ispcr.5 which triggers an software reset and makes cpu reboot into application program memory (ap - memory) on the address 0x0000. as we have known , the purpose of the isp code is to program both ap - memory and iap - memory. therefore, the mcu must boot from the isp - memory in order to execute the isp code . there are two methods to implement in - system programming according to how the mcu boots from the i sp- memory. 26.3.1. hardware approached isp to make the mcu directly boot from the isp - memory when it is just powered on, the mcu?s hardware option s hwbs and isp memory must be enabled. the isp entrance method by hardware option is named hardware approached. onc e hwbs and isp memory are enabled, the mcu will always boot from the isp - memory to execute the isp code ( boot loader program) when it is just powered on. the first thing the isp code should do is to check if there is an isp request. if there is no isp requ ested, the isp code should trigger a software reset (setting ispcr.7~5 to ? 101 ? simultaneously) to make the mcu re - boot from the ap - memory to run the user?s application program.. if the additional hardware option, hwbs2, is enabled with hwbs and isp memor y , the mcu will always boot from isp memory after power - on or external reset finish ed. it provides another hardware approached way to enter isp mode by external reset signal. after first time power - on, mg82fg5bxx can perform isp operation by external reset trigger and doesn?t wait for next time power - on, which suits the non - power - off system to apply the hardware approached isp function. 26.3.2. software approached isp the software approached isp to make the mcu boot from the isp - memory is to trigger a software r eset while the mcu is running in the ap - memory. in this case, ne ither hwbs nor hwbs2 is enabled . the only way for the mcu to boot from the isp - memory is to trigger a software reset , setting ispcr.7~5 to ? 111 ? simultaneously, when running in the ap - memor y. note: the isp memory must be configured a valid space by hardware option to reserve isp mode for software approached isp application.
megawin mg82fg5b xx data sheet 231 26.3.3. notes for isp developing of the isp code although the isp code is programmed in the isp - memory that has an isp start address in the mcu?s flash (see figure 26? 1 for mg82fg5b32 ), it doesn?t mean you need to put this offset (= isp start address ) in your source code. the code offset is automatically manipulated by the hardware. user just need s to develop it like an application program in the ap - memory. interrupts during isp after triggering the isp /iap flash processing, the mcu will halt for a while for internal isp processing until the processing is completed. at this time, the in terrupt will queue up for being serviced if the interrupt is enabled previously. once the processing is completed, the m c u continues running and the interrupts in the queue will be serviced immediately if the interrupt flag is still active. the user, howev er, should be aware of the following: (1) any interrupt can not be in - time serviced when the mcu halts for isp processing. (2) the low /high - level triggered external interrupts, n intx, should keep activated until the isp is completed, or they will be negle cted. isp and i dle mode mg82fg5bxx does not make use of idle - mode to perform isp function . instead, it freezes cpu running to release the flash memory for isp /iap engine operating . once isp /iap operation finished , cpu will be resumed and advanced to the instruction which follows the previous instruction that invokes isp /iap activity. accessing destination of isp as mentioned previously, the isp is used to program both the ap - memory and the iap - memory. once the accessing destination address is beyond th at of the last byte of the iap - memory, the hardware will automatically neglect the triggering of isp processing. that is the triggering of isp is invalid and the hardware does nothing. flash endurance for isp the endu rance of the embedded flash is 2 0,000 erase/write cycles, that is to say, the erase - then - write cycles shouldn?t exceed 2 0,000 times. thus the user should pay attention to it in the application which needs to frequently update the ap - memory and iap - memory.
232 mg82fg5b xx data sheet megawin 26.4. iap operation the mg82fg5bxx has built a function as in application programmable (iap), which allows some region in the flash memory to be used as non - volatile data storage while the application program is running. this useful feature can be applied to the application where the data must be kept after power off. thus, there is no need to use an external serial eeprom (such as 93c46, 24c01, .., and so on) for saving the non - volatile data. in fact, the operating of iap is the same as that of isp except the flash range to be programmed is d ifferent. the programmable flash range for isp operating is located within the ap and iap m emory, while the range for iap operating is only located within the configured iap - memory. note: (1) for mg82fg5bxx iap feature, the software should specify an iap - memory space by writing iaplb in page - p sfr space. the iap - memory space can be also configured by a universal writer / programmer or megawin proprietary writer/programmer which configuration is corresponding to iaplb initial value. (2) the program code to e xecute iap is located in the ap - memory and just only program iap - memory not isp - memory. 26.4.1. iap - memory boundary/range if isp - memory is specified, t he range of the i ap- memory is determined by iap and the isp starts address as listed below. iap high boundary = isp start address ? 1. iap low boundary = isp start address ? iap size . if isp - memory is not specified, the range of the iap - memory is determined by the following formula. iap high boundary = 0x 7 fff . iap low boundary = 0x 7 fff ? iap size + 1. for examp le, if isp - memory is 1k , so that isp start address is 0x 7 c 00 , and iap - memory is 1k , then the iap - m emory range is located at 0x 7 800 ~ 0x 7 b ff . the iap low boundary in mg82fg5b32 is defined by iaplb register which can be modified by software to adjust the iap size in user ? s ap program. 26.4.2. update data in iap - memory the special function registers are related to isp /iap would be shown in section ? 26.5 isp/iap register ? . becau se the iap - memory is a part of flash memory, on ly page erase, no byte erase , is provided for flash erasing. to update ?one byte? in the iap - memory, users can not directly program the new datum into that byte . the following steps show the proper procedure: step 1 : save the whole page flash data (with 512 bytes) into xram buffer which contains the data to be updated. step 2 : erase this page ( using isp/iap flash page erase mode ) . step 3: modify the new data on the byte(s) in the xram buffer. step 4 : program t he updated data out of the xram buffer into this page ( using isp/iap flash program mode ) . to read the data in the iap - memory, users can use the isp/iap flash r ead mode to get the targeted data .
megawin mg82fg5b xx data sheet 233 26.4.3. notes for iap interrupts during iap after triggering th e isp /iap flash processing for in - application programming, the mcu will halt for a while for internal i a p processing until the processing is completed. at this time, the interrupt will queue up for being serviced if the interrupt is enabled previously. onc e the processing is completed, the mcu continues running and the interrupts in the queue will be serviced immediately if the interrupt flag is still active. users, however, should be aware of the following: (1) any interrupt can not be in - time serviced du ring the mcu halts for i a p processing. (2) the low /high - level triggered external interrupts, n intx, should keep activated until the i a p is completed, or they will be neglected. iap and i dle mode mg82fg5bxx does not make use of idle - mode to perform iap fu nction . instead, it freezes cpu running to release the flash memory for isp/iap engine operating . once isp /iap operation finished , cpu will be resumed and advanced to the instruction which follows the previous instruction that invokes isp /iap activity. a ccessing destination of iap as mentioned previously, the iap is used to program only the iap - memory. once the accessing destination is not within the iap - memory, the hardware will automatically neglect the triggering of i a p processing. that is the trigger ing of i a p is invalid and the hardware does nothing. an alternative method to read iap data to read the flash data in the iap - memory, in addition to using the flash read mode, the alternative method is using the instruction ?movc a,@a+dptr?. where, dptr and acc are filled with the wanted address and the offset, respectively. and, the accessing destination must be within the iap - memory, or the read data will be indeterminate. note that using ?movc? instruction is much faster than using the flash read mode. flash endurance for iap the endurance of the embedded flash is 2 0,000 erase/write cycles, that is to say, the erase - then - write cycles shouldn?t exceed 2 0,000 times. thus the user should pay attention to it in the application which needs to frequently up date the iap - memory.
234 mg82fg5b xx data sheet megawin 26.5. isp/iap register the following special function registers are related to the access of isp , iap and page - p sfr : ifd: isp/iap flash data register sfr page = 0~f sfr address = 0xe2 reset = 1111 - 1111 7 6 5 4 3 2 1 0 r/ w r/w r/w r/w r/w r/w r/w r/w ifd is the data port register for isp/iap /page - p operation. the data in ifd will be written into the desired address in operating isp/iap /page - p write and it is the data window of readout in operating isp/iap /page - p read. ifadrh: isp/iap address for high - byte addressing sfr page = 0~f sfr address = 0xe3 reset = 0000 - 0000 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w ifadrh is the high - byte address port for all isp/iap modes. it is not defined in page - p mode . ifadrl: isp/iap address for low - byte addressing sfr page = 0~f sfr address = 0xe4 reset = 0000 - 0000 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w ifadrl is the low byte address port for all isp/iap /page - p modes. in flash page erase ope ration, it is ignored. ifmt: isp/iap flash mode table sfr page = 0~f sfr address = 0xe5 reset = xxxx - x000 7 6 5 4 3 2 1 0 -- -- -- -- -- ms.2 ms.1 ms.0 w w w w w r/w r/w r/w b it 7 ~4 : reserved . software must write ? 0 000_0 ? on these bits when ifmt i s written. bit 3~0: isp/iap/page - p operating mode selection ms.2~0 mode 0 0 0 standby 0 0 1 flash byte read of ap /iap - memory 0 1 0 flash byte program of ap /iap - memory 0 1 1 flash page erase of ap/iap - memory 1 0 0 page p sfr write 1 0 1 page p sfr read others reserved ifmt is used to select the flash mode for performing num erous isp/iap functi on or to select page p sfr access .
megawin mg82fg5b xx data sheet 235 scmd : sequential command data register sfr page = 0~f sfr address = 0xe6 reset = xxxx - xxxx 7 6 5 4 3 2 1 0 s cmd r/w r/w r/w r/w r/w r/w r/w r/w scmd is the command port for triggerin g isp/iap/ page - p act ivity. if scmd is filled with sequential 0x46h, 0xb9h and if ispcr.7 = 1, isp /iap/page - p activity will be triggered. ispcr : is p control register sfr page = 0~f sfr address = 0xe7 reset = 0000 - xxxx 7 6 5 4 3 2 1 0 ispen swbs swrst cfail -- - - - - - - r/w r/w r/w r/w w w w w b it 7: ispen, isp/iap/page - p operation enable. 0 : global disable all isp /iap/page - p program/erase/read function. 1 : enable isp /iap/page - p program/erase/read function. b it 6: swbs, software boot selection control. 0 : boot from main - memor y after reset . 1 : boot from isp memory after reset . b it 5: swrst, software reset trigger control. 0 : no operation 1 : ge nerate software system reset. it will be cleared by hardware automatically. b it 4: cfail, command fail indication for isp/iap operation. 0 : the last isp/iap command has finished successfully. 1 : the last isp/iap command fails. it could be caused since the access of flash memory was inhibited. b it 3~0 : reserved . software must write ? 0 ? on these bits when ispcr is written. ckcon 1 : clock control register 1 sfr page = 0~f & p sfr address = 0xbf reset = 0 x00 - 0000 7 6 5 4 3 2 1 0 xtor -- xcks5 xcks4 xcks3 x cks2 x cks1 x cks0 r w r /w r /w r /w r/w r/w r/w bit 5 ~0: this is set the oscin frequency value to define the time base of isp/iap programming. fill with a proper value according to oscin, as listed below. [xcks 5 ~xcks0] = oscin ? 1 , w here oscin=1~ 40 (mhz ) . for examples, (1) if oscin=12mhz, then fill [xcks 5 ~xcks0] with 11, i.e., 0 0 - 1011b. (2) if oscin=6mhz, then fill [xcks 5 ~xcks0] with 5, i.e., 0 0 - 0101b. oscin xcks [4:0] 1mhz 0 0 - 0000 2mhz 0 0 - 0001 3mhz 0 0 - 0010 4mhz 0 0 - 0011 ?? ?? ?? ??
236 mg82fg5b xx data sheet megawin 38mhz 10 - 0101 39mhz 10 - 0110 40mhz 10 - 0111 iaplb : iap low boundary sfr page = p only sfr address = 0x03 reset = 0 111- 0000 7 6 5 4 3 2 1 0 iaplb [7:1] 0 r/ w r/ w r/ w r/ w r/ w r/ w r/ w w b it 7 ~ 0: the iaplb determines the iap - memory lower boundary. since a flash pag e has 512 bytes, the iaplb must be an even number. to read iaplb, mcu need to define the imft for mode selection on iaplb read and set ispcr.ispen. and then write 0x46h & 0xb9h sequentially into scmd. the iaplb content is available in ifd. if write iaplb, mcu will put new iaplb setting value in ifd firstly. and then select imft, enable ispcr.ispen and then set scmd. the iaplb content has already finished the updated sequence. the range of the iap - memory is determined by iaplb and the isp start address as l isted below. iap lower boundary = iaplb [7:0] x 256, and iap higher boundary = isp start address ? 1. for example, if iaplb=0x 6 0 and isp start address is 0x 7 0 00, then the iap - memory range is located at 0x 6 0 00 ~ 0x 6 f ff. additional attention point, the ia p low boundary address must not be higher than isp start address.
megawin mg82fg5b xx data sheet 237 26.6. sample code for isp the following figure 26 ? 8 shows a sample code for isp operation. figure 26? 8 . sample code for isp ;****************************************************************************************** ; demo program for the isp ;****************************************************************************************** ifd data 0e2h ifadrh data 0e3h ifadrl data 0e4h i fm t data 0e5h scmd data 0e6h ispcr data 0e7h ; mov ispcr,#10000 000 b ; ispcr.7=1, enable isp ;============================================================= ================ ; 1. page erase mode ( 512 bytes per page) ;============================================================================= orl i fmt ,#03h ; ms [2: 0]=[ 0, 1,1], select page erase mode mov ifadrh,?? ;fill page address in ifadrh & ifadrl mov ifadrl,?? ; mov scmd,#46h ;trigger isp processing mov scmd,#0b9h ; ;now in processing...(cpu will halt here until complete) ;======================================================= ====================== ; 2. byte program mode ;============================================================================= orl i fmt ,#02h ; ms [2: 0]=[ 0, 1,0], select byte program mode anl i spcr ,#0 f ah ; mov ifadrh,?? ;fill byte address in ifadrh & ifadrl mov ifadrl,?? ; mov ifd,?? ;fill the data to be programmed in ifd mov scmd,#46h ;trigger isp processing mov scmd,#0b9h ; ;now in processing...(cpu will halt here until complete) ;============================================================================= ; 3. verify using read mode ;============================================================================= anl i fmt ,#0 f 9 h ; ms1 [2 :0 ]=[ 0, 0,1], select byte read mode orl i fmt ,#0 1 h ; mov ifadrh,?? ;fill byte address in ifadrh & ifadrl mov ifadrl,?? ; mov scmd,#46h ;trigger isp processing mov scmd,#0b9h ; ;now in processing...(cpu will halt here until complete) mov a,ifd ;data will be in ifd cjne a, wanted,isp_error ; compare with the wanted value ... isp_error: ... ;
238 mg82fg5b xx data sheet megawin 27. page p sfr access mg82fg5bxx builds a sp ecial sfr page (page p) to store the control registers for mcu operation. these sfrs can be accessed by the isp/iap operation with different ifmt. in page p access, ifadrh must set to ? 00 ? and ifadrl indexes the sfr address in page p. if ifmt= 04h for page p writing, the content in ifd will be loaded to the sfr in ifadrl indexed after the scmd triggered. if ifmt = 05h for page p reading, the content in ifd is stored the sfr value in ifadrl indexed after the scmd triggered. following descriptions are the sf r function definition in page p: iaplb : iap low boundary sfr page = p sfr address = 0x03 reset = 0 111- 0 000 7 6 5 4 3 2 1 0 iaplb [7:1] 0 r/ w r/ w r/ w r/ w r/ w r/ w r/ w w b it 7 ~ 0: the iaplb determines the iap - memory lower boundary. since a flash page ha s 512 bytes, the iaplb must be an even number. to read iaplb, mcu need to define the ifadrl for sfr address in page - p, the imft for mode selection on page - p read and set ispcr.ispen. and then write 0x46h & 0xb9h sequentially into scmd. the iaplb content is available in ifd. if write iaplb, mcu will put new iaplb setting value in ifd firstly. and index ifadrl, select imft, enable ispcr.ispen and then set scmd. the iaplb content has already finished the updated sequence. the range of the iap - memory is determ ined by iaplb and the isp s tart address as listed below. iap lower boundary = iaplb [7:0] x 256, and iap higher boundary = isp start address ? 1. for example, if iaplb=0x 6 0 and isp start address is 0x 7 0 00, then the iap - memory range is located at 0x 6 0 00 ~ 0x 6 f ff. additional attention point, the iap low boundary address must not be higher than isp start address. ckcon 2 : clock control register 2 sfr page = p sfr address = 0x40 reset = 0 1 01- 0000 7 6 5 4 3 2 1 0 xtgs1 xtgs0 xtale ihrcoe mcks1 mcks0 oscs 1 oscs0 r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w bit 7~6: xtgs1~xtgs0, xtal oscil l ator gain control register. software m ust writ ?01? on the two bits. xtgs1 , xtgs 0 gain define 0, 0 gain for 32.768k 0 , 1 gain for 2mhz ~ 25mhz others reserved bit 5: xtale, e xternal crystal(xtal) enable. 0: disable xtal oscillating circuit. in this case, xtal2 and xtal1 behave as port 6.0 and port 6.1. 1: enable xtal oscillating circuit. if this bit is set by cpu software , software pools the xtor (ckcon1.7) true to indicate th e crystal oscillator is ready for oscin clock selected. bit 4: ihrcoe, internal high frequency rc oscillator enable. 0: disable internal high frequency rc oscillator. 1: enable internal high frequency rc oscillator. if this bit is set by cpu software, it needs 32 us to ha ve stable output after ihrcoe is enabled.
megawin mg82fg5b xx data sheet 239 bit 3~2: mcks[1:0], mck source selection. mcks [ 1 :0] mck source selection oscin =12mhz ckmis = [01 ] oscin =11.059mhz ckmis = [01 ] 0 0 oscin 12mhz 11.059mhz 0 1 ckmi x 4 (enckm =1) 24mhz 22.1 18mhz 1 0 ckmi x 5.33 (enckm =1) 32mhz 29.491mhz 1 1 ckmi x 8 (enckm =1) 48mhz 44.236mhz bit 1~0: osc[1:0], oscin source selection. ckmis [ 1 :0] oscin source selection 0 0 ihrco 0 1 xtal 1 0 ilrco 1 1 ecki, external clock input (p6.0) as oscin. ckcon 3 : clock control register 3 sfr page = p only sfr address = 0x41 reset = 0000 - 0010 7 6 5 4 3 2 1 0 0 0 fwkp 0 mckd1 mckd0 mcds1 mcds0 w w r /w w r/w r/ w r/w r/w pcon2: power control register 2 sfr page = p only sfr address = 0x44 por = 0 0 11- 0101 7 6 5 4 3 2 1 0 awbod1 0 bo1s1 bo1s0 bo1re ebod1 bo0re 1 r/ w w r/ w r/ w r/ w r/ w r/ w w bit 7: awbod1, awaked bod1 in pd mode. 0: bod1 is disabled in power - down mode. 1: bod1 keeps operation in power - down mode. bit 6: reserved. software must wri te ? 0 ? on this bit when dcon0 is written. bit 5~4: bo1s[1:0]. brown - out detector 1 monitored level selection. t he initial values of these two bits are loaded from or1.bo1s1o and or1.bo1s0o. bo1s [ 1 :0] bod1 detecting level 0 0 2.0v 0 1 2.4v 1 0 3.7v 1 1 4.2v bit 3: bo1re, bod1 reset enabled. 0: disable bod1 to trigger a system reset when bof1 is set. 1: enable bod1 to trigger a system reset when bof1 is set. bit 2: ebod1, enable bod1 that monitors vdd power dropp ed at a bo1s1~0 specified voltage l e vel. 0: disable bod1 to slow down the chip power consumption. 1: enable bod1 to monitor vdd power dropped. bit 1: bo0re, bod0 reset enabled. 0: disable bod0 to trigger a system reset when bof0 is set. 1: enable bod0 to trigger a system reset when bof0 is set (vdd meets 2.2v). bit 0: reserved. software must write ? 1 ? o n this bit when pcon2 is written.
240 mg82fg5b xx data sheet megawin spcon0: sfr page control 0 sfr page = p only sfr address = 0x48 por = 0 000 - 0000 7 6 5 4 3 2 1 0 rtcctl p6ctl p4ctl wrctl ckctl1 ckctl0 pwctl1 pwctl0 w r/ w r/ w r/ w r/ w r/ w r/ w r/ w bit 7: rtcctl. rtccr sfr access control. if rtcctl is set, it will disable the rtccr sfr modified in general page. rtccr in general page only keeps the sfr read function. but software always owns the modification capability in sfr page p. bit 6: p6ctl. p6 sfr access control. if p6ctl is set, it will disable the p6 sfr modified in page 0~f . p6 in page 0~f only keeps the sfr read function. but software always owns the modification capability in sfr page p. bit 5: p4ctl. p4 sf r access control. if p4ctl is set, it will disable the p4 sfr modified in page 0~f. p4 in page 0~f only keeps the sfr read function. but software always owns the modification capability in sfr page p. bit 4: wrctl. wdtcr sfr access control. if wrctl is se t, it will disable the wdtcr sfr modified in page 0~f. wdtcr in page 0~f only keeps the sfr read function. but software always owns the modification capability in sfr page p. bit 3: ckctl1. ckcon1 sfr access control. if ckctl1 is set, it will disable the ckcon1 sfr modified in page 0~f. ckcon1 in page 0~f only keeps the sfr read function. but software always owns the modification capability in sfr page p. bit 2: ckctl0. ckcon0 sfr access control. if ckctl0 is set, it will disable the ckcon0 sfr modified i n page 0~f. ckcon0 in page 0~f only keeps the sfr read function. but software always owns the modification capability in sfr page p. bit 1: pwctl1. pcon1 sfr access control. if pwctl1 is set, it will disable the pcon1 sfr modified in page 0~f. pcon1 in pa ge 0~f only keeps the sfr read function. but software always owns the modification capability in sfr page p. bit 0: pwctl0. pcon0 sfr access control. if pwctl0 is set, it will disable the pcon0 sfr modified in page 0~f. pcon0 in page 0~f only keeps the sf r read function. but software always owns the modification capability in sfr page p. dcon0: device control 0 sfr page = page p only sfr address = 0x4c reset = 0000 - 0011 7 6 5 4 3 2 1 0 0 iapo 0 0 0 iorctl rstio ocde w r/ w w w w r/ w r/ w w bit 0: re served. software must write ? 0 ? o n this bit when dcon0 is written. bit 6: iapo, iap function only. 0: maintain iap region to service iap function and code execution. 1: disable the code execution in iap region and the region only service iap function. bi t 4~3: reserved. software must write ? 0 ? on these bits when dcon0 is written. bit 2: iorctl, gpio reset control. 0: port 6 keeps reset condition for all reset events. 1: if this bit is set, port 6 is only reset by por/ext - reset/bor0/bor1 (if bo0re or bo1r e is enabled). bit 1: rstio, rst function on i/o, 0: select i/o pad function for p47.
megawin mg82fg5b xx data sheet 241 1: select i/o pad function for external reset input, rst. bit 0: oc de, ocd enable. 0: disable ocd interface on p4.4 and p4.5 1: enable ocd interface on p4.4 and p4.5.
242 mg82fg5b xx data sheet megawin 27.1. page p sfr access sample code ( 1 ). required function: general function call of page - p sfr read assembly code example: _ page_p_sfr_read: page_p_sfr_read: mov ifadrh,000h mov ifmt,#(ms2|ms0) ; pagep_read=0x05 anl ispcr,#cfail ; orl ispcr,#ispen ; enable function mov scmd,#046h ; mov scmd,#0b9h ; mov ifmt,#000h ; flash_standby=0x00 anl ispcr,#~ispen ; disable function ret c code example: void page_p_sfr_read (void) { ifadrh = 0x00; // ispcr = ispen; // enable function ifmt = (ms0 | ms2); // pagep_read=0x05 scmd = 0x46; // scmd = 0xb9; // ifmt = flash_standby; // flash_standby=0x00 ispcr &= ~ispen; } (2). required function: genera l function call of page - p sfr write assembly code example: _ page_p_sfr_write: page_p_sfr_write: mov ifadrh,000h ; mov ispcr,#ispen ; enable function mov ifmt,#ms2 ; pagep_wri te=0x04 mov scmd,#046h ; mov scmd,#0b9h ; mov ifmt,#000h ; flash_standby=0x00 anl ispcr,#~ispen ; disable function ret c code example: void page_p_sfr_write (void) { ifadrh = 0x00; ispcr = ispen; // enable function ifmt = ms2; // pagep_write=0x04 scmd = 0x46; // scmd = 0xb9; //
megawin mg82fg5b xx data sheet 243 ifmt = flash_standby; // flash_standby=0x00 ispcr &= ~ispen; } ( 3 ). required function: e nable pwctl0 for p con0.pd control in page - p assembly code example: mov ifadrl,#spcon0 ; call page_p_sfr_read ; orl ifd,#pwctl0 ; set pwctl0 call page_p_sfr_write ; mov ifd,pcon0 ; read pcon0 orl ifd,#pd ; w rite pcon0 and power - down mov ifadrl,#pcon0_p ; call page_p_sfr_write ; c code example: ifadrl = spcon0; // page_p_sfr_read(); // ifd |= pwctl0; // set pwctl0 page_p_sfr_write(); // ifd = pcon0; // read pcon0 ifd |= pd; // write pcon0 ifadrl = pcon0_p; // page_p_sfr_write(); // ( 4 ). required function: enable ckctl0 for sysclk divider (ckcon0) changed in page - p assembly code example: mov ifadrl,#spcon0 ; call page_p_sfr_read ; orl ifd,#ckctl0 ; set ckctl0 call page_p_sfr_write ; mov ifd,ckcon0 ; read ckcon0 orl ifd,#(afs | scks0) ; write ckcon0 a nd set afs mov ifadrl,#ckcon0_p ; sysclk / 2 call page_p_sfr_write c code example: ifadrl = spcon0; // page_p_sfr_read (); // ifd |= ckctl0; // set ckctl page_p_sfr_write(); // ifd = ckcon0; // read ckcon0 ifd |= (afs | scks0); // ifadrl = ckcon0_p; // page_p_sfr_write(); // write ckcon0
244 mg82fg5b xx data sheet megawin 28. auxiliary sfrs auxiliary register 0 sfr page = 0 ~ f sfr address = 0xa1 reset = 000 0 - 0000 7 6 5 4 3 2 1 0 p60 o c1 p60 oc 0 p60fd t0xl p4fs1 p4fs0 int1h int0h r/w r/w r/w r/ w r/w r/w r/w r/w bit 7~6: p6.0 functi on configured control bit 1 and 0. the two bits only act when internal rc oscillator (ihrco or ilrco) is selected for system clock source. in crystal mode, xtal2 and xtal1 are the alternated function of p6.0 and p6.1. in external clock input mode, p6.0 is the dedicated clock input pin . in internal oscillator condition, p6.0 provides the following selections for gpio or clock source generator. when p60oc[1:0 ] index to non - p6.0 gpio function, p6.0 will drive the on - chip rc oscillator (ihrco or ilrco) output t o provide the clock source for other devices. p60oc[1:0] p60 function i/o mode 00 p60 by p6m0.0 01 mck/1 by p6m0.0 10 mck/2 by p6m0.0 11 mck/4 by p6m0.0 please refer section ? 9 system clock ? to get the more detailed clock information. for clock - out on p 6 .0 function, it is recommended to set p 6 m0.0 to ? 1 ? which selects p 6 .0 as push - push output mode. bit 5: p60fd, p6.0 fast driving. 0: p6.0 output with default drivin g. 1: p6.0 output with fast driving enabled. if p6.0 is configured to clock output, enable this bit when p6.0 output frequency is more than 12mhz at 5v application or more than 6mhz at 3v application. bit 3~2: p4.4 and p4.5 alternated function selection. p4fs[1:0] p4.4 p4.5 00 p4.4 p4.5 01 rxd0 txd0 10 t0/t0cko t1/t1cko 11 t2ex t2/t2cko bit 1: int1h, int1 high/rising trigger enable. 0: remain int1 triggered on low level or falling edge on nint1 port pin . 1: set int1 triggered on high level or rising edge on nint1 port pin . bit 0: int0h, int0 high/rising trigger enable. 0: remain int0 triggered on low level or falling edge on nint0 port pin . 1: set int0 triggered on h igh level or rising edge on nint0 port pin . auxr1 : auxiliary control register 1 sfr page = 0~f sfr address = 0xa2 reset = 0000 - 0000 7 6 5 4 3 2 1 0 p1kbih p3kbil p4spi p3s1 p3s1mi p6twi 0 p3cex dps r/w r/w r/w r/w r /w r /w r /w r/w bit 7: p1kbih, kbi high nibble port selection on p1.3, p1.2, p1.1 and p1.0. p1kbih kbi.7~4 0 p2.6, p2. 4, p2.3, p2.2 1 p1.3, p1.2, p1.1, p1.0
megawin mg82fg5b xx data sheet 245 bit 6: p3kbil, kbi low nibble port selection on p3.5, p3.4, p3.1 and p3.0. p3kbil kbi.3~0 0 p2.7, p2.5, p2.1, p2.0 1 p3.5, p3.4, p3.1, p3.0 bit 5: p4spi, spi interface on p4.1~p4.0 and p2.1~p2.0. p4spi nss m osi miso spiclk 0 p1.4 p1.5 p1.6 p1.7 1 p2.0 p2.1 p4.1 p4.0 bit 4: p3s1, serial port 1 (uart1) function on p3.3 and p3.4 if p3cex is disabled. p3s1 rxd1 txd1 0 p1.2 p1.3 1 p3.3 p3.4 bit 3: p3s1mi, s1mi function on p3.5. p3s1mi s1mi 0 p1.0 1 p3.5 bit 2: p6twi 0 , twi 0 function on p6. the function is valid when p60oc[1:0] is equal to ? 00? . p6twi 0 twi 0 _scl twi 0 _sda 0 p4.0 p4.1 1 p6.0 p6.1 bit 1: p3cex, cex5, cex3 and cex1 function on p3.5, p3.4 and p3.3. p3cex cex5 cex3 cex1 0 p2.7 p2.5 p2.3 1 p3.5 p3.4 p3.3 bit 0: dps, dual dptr selector. 0: select dptr0. 1: select dptr1. auxr2: auxiliary register 2 sfr page = 0~f sfr address = 0xa3 reset = 0000 - 0000 7 6 5 4 3 2 1 0 int3is1 int3is0 int2is1 int2is0 t1x12 t0x12 t1ckoe t0ckoe r/w r/w r/w r/w r/w r/w r/w r/w bit 7~6: int3is1~0, nint3 input selection bits which function is defined as following table. int3is1~0 nint3 00 p4.5 01 p2.1 10 p1.5 11 p6.0 bit 5~4: int2is1~0, nint2 input selection bits which function is defined as following t able. int2is1~0 nint2 00 p4.4 01 p2.0 10 p1.4 11 p6.1 bit 3: t1x12 , timer 1 clock sour ce select or while c/t=0. 0: c lear to select sysclk /12.
246 mg82fg5b xx data sheet megawin 1: set to select sysclk as the clock source . bit 2: t 0 x12 , timer 1 clock sour ce select or while c/t=0. 0: c le ar to select sysclk /12. 1: set to select sysclk as the clock source . bit 1: t1ckoe, timer 1 clock output enable. 0: disable timer 1 clock output. 1: enable timer 1 clock output on p3.5. bit 0: t0ckoe, timer 0 clock output enable. 0: disable timer 0 clock output. 1: enable timer 0 clock output on p3.4. auxr3: auxiliary register 3 sfr page = 0~f sfr address = 0xa4 reset = 0000 - 0000 7 6 5 4 3 2 1 0 staf stof bpoc1 bpoc0 gf p1s0mi p3eci p3twi1 r/w r/w r/w r/w r/w r/w r/w r/w bit 7: staf, start flag d etection of s twi. 0: clear by firmware by writing ? 0 ? on it. 1: set by hardware to indicate the start condition occurred on s twi bus. bit 6: stof, stop flag detection of s twi. 0: clear by firmware by writing ? 0 ? on it. 1: set by hardware to indicate the s tart condition occurred on s twi bus. bit 3 : r eserved. software must write ? 0 ? on this bit when auxr3 is written. bit 5 ~ 4 : bpoc1~0, beeper output control bits. bpoc[1:0] p4.4 function i/o mode 00 p4.4 b y p4m0.4 01 ilrco/64 b y p4m0.4 10 ilrco/32 b y p4m0 .4 11 ilrco/16 b y p4m0.4 for beeper on p 4 . 4 function, it is recommended to set p 4 m0. 4 to ? 1 ? which selects p 4 . 4 as push - push output mode. bit 2: p1s0mi, s0mi function on p1.6. p1s0mi s0mi 0 p3.2 1 p1.6 bit 1: p3eci, eci function on p3.2. p3eci eci 0 p2.1 1 p3.2 bit 0: p3twi1, twi1 function on p3. p3twi1 twi1_scl twi1_sda 0 p1.0 p1.1 1 p3.0 p3.1
megawin mg82fg5b xx data sheet 247 sfrpi: sfr page index register sfr page = 0~f & p sfr address = 0xac reset = xx xx- 0000 7 6 5 4 3 2 1 0 -- -- -- -- pidx3 pidx2 pidx1 pidx0 w w w w r/w r/w r/w r/w bit 7 ~4: reserved. software must write ? 0 ? on these bits when sfrpi is written. bit 3~0: sfr page index. the available pages are only page ? 0 ? and ? 1 ? . pidx [ 3 :0] selected page 0000 page 0 0001 page 1 0010 page 2 0011 page 3 ?? ?? ?? ?? ?? ?? 1111 page f
248 mg82fg5b xx data sheet megawin 29. hardware option the mcu?s hardware option defines the device behavior which cannot be programmed or controlled by software. the hardware options can only be programmed by a universal programmer, the ?megawin 8051 w ri ter u1 ? or the ?megawin 8051 ice adapter ? (the ice adapter also supports icp programm ing function. refer section ? 30.5 in - chip - programming function ? ) . after whole - chip e rased, all the hardware options are left in ?disabled? state and there is no isp - memory and iap - memory configured. the mg82fg5bxx has the following hardware options: lock: ?: e nabled . code dumped on a universal writer or programmer is locked to 0xff for security. ? : d isabled . not locked. isp - memory space : the isp - memory (boot loader) space is specified by its starting address. and, its higher boundary is limited by the flash end address, i.e., 0x 7 fff. the following table lists the isp space option in th is chip. in default setting, mg82fg5b32 isp space is configured to 1 .5k that had been embedded megawin proprietary combo isp code to perform d evice f irmware upgrade through megawin 1 - line isp protocol and com port isp. isp - memory size isp start address 4 k bytes 0x 7 0 00 3 .5 k bytes 0x 7 2 00 3 k bytes 0x 7 4 00 2 .5 k bytes 0x 7 6 00 2 k bytes 0x 7 8 00 1 .5 k bytes 0x 7 a 00 1 k bytes 0x 7 c 00 no isp space - - hwbs: ?: e nabled . when powered up, mcu will boot from isp - memory if isp - memory is configured. ? : d isabled . mcu a lways boots from ap - memory. hwbs2: ?: e nabled . not only power - up but also any reset will cause mcu to boot from isp - memory if isp - memory is configured . ? : d isabled . where mcu boots from is determined by hwbs. i a p - memory space : the i a p - memory space spe cifie s the user defined iap space. the iap - memory space can be configured by hardware option or mcu software by modifying iaplb. in default, it is configured to 2.5 k bytes. bo1s1o, bo1s0o : ?, ?: select bod1 to detect 2.0v. ?, ? : select bod1 to detect 2.4v. ? , ? : select bod1 to detect 3.7v. ? , ? : select bod1 to detect 4.2v. bo0reo : ?: e nabled . bod 0 will trigger a reset event to cpu on ap program start address. (2.2v) ? : d isabled . bod 0 cannot trigger a reset to cpu. b o 1reo : ? : enabled. bod 1 will trigger a reset event to cpu on ap program start address. (4.2v, 3.7v, 2.4v or 2.0v) ? : d isabled . bod 1 cannot trigger a reset to cpu. w reno : ?: e nabled . set wdtcr.wren to enable a system reset function by wdtf.
megawin mg82fg5b xx data sheet 249 ? : d isabled . clear wdtcr.wren to disable the system reset function by wdtf. nswdt : non - stopped wdt ?: e nable d. set wdtcr.nsw to enable the wdt running in power down mode (watch mode) . ? : d isable d. clear wdtcr.nsw to disable the wdt running in power down mode (d isable w atch mode ) . hwenw : hardware loaded for ? enw ? of wdtcr. ?: e nable d. e nable wdt and load the content of wreno, nswdt, hwwidl and hwps2 ~ 0 to wdtcr after power - on . ? : d isable d. wdt is not enabled automatically after power - on. hwwidl, hwps2, hwps1, hwps0 : when hwenw is enabled , the content o n these four fused bits will be loaded to wdtcr sfr after power - on. wdsfwp : ?: e nable d. the wdt sfr s, wren, nsw, widl, ps2, ps1 and ps0 in wdtcr , will be write - protected. ? : d isable d. the wdt sfr s, wren, nsw, widl, ps2, ps1 and ps0 in wdtcr , are free fo r writing of software.
250 mg82fg5b xx data sheet megawin 30. application notes 30.1. power supply circuit to have the mg82fg5bxx work with power supply varying from 2. 0 v to 5.5v, adding some external decoupling and bypass capacitor s is necessary, as shown in figure 30? 1 . figure 30? 1 . power supplied circuit vdd vr 0 vss power supply 0 . 1 uf 4 . 7 uf mcu 0 . 1 uf 10 uf 30.2. reset circuit normally, the power - on reset can be successfully generated during power - up. however, to further ensure the mcu a reliable reset d uring power - up, the external reset is necessary. figure 30 ? 2 shows the external reset circuit, which consists of a capacitor c ext connected to vdd (power supply) and a resistor r ext connected to vss (ground). in g eneral, r ext is optional because the rst pin has a n internal pull - down resistor (r rst ). this internal diffused resistor to vss permits a power - up reset using only an external capacitor c ext to v dd. see section ? 31.2 dc characteristics ? for r rst value. figure 30? 2 . reset circuit vdd rst vss power supply mcu r rst r ext (optional) c ext 4.7uf 47k?
megawin mg82fg5b xx data sheet 251 30.3. xtal oscillating circuit t o achieve successful and exact oscillating (up to 24mhz) , the capacitors c1 and c2 are necessary, as shown in figure 30? 3 . normally, c1 and c2 have the same value. table 30? 1 lists the c1 & c2 value for the different frequency crysta l application. figure 30? 3 . xtal oscillating circuit crystal xtal 1 mcu c1 xtal2 c2 table 30 ? 1 . reference capacitance of c1 & c2 for crystal oscillating circuit crystal c1, c2 capacitan ce 16mhz ~ 25mhz 10pf 6mhz ~ 16mhz 15pf 2mhz ~ 6mhz 33pf
252 mg82fg5b xx data sheet megawin 30.4. icp and ocd interface circuit mg82fg5bxx devices include an on - chip megawin proprietary debug interface to allow in - chip - p rogramming (icp) and i n - system on - chip - d ebugging (ocd) with the produ ction part installed in the end application. the i c p and ocd share the same interface to use a clock signal ( icp_scl/ocd_scl ) and a bi - directional data signal ( icp_sda/o cd _sda ) to transfer information between the device and a host system. the icp interfac e allows the icp_scl/icp_sda pins to be shared with user functions so that in - chip flash programming function could be performed. this is practicable because icp communication is performed when the device is in the halt state, where the on - chip peripherals and user software are stalled. in this halted state, the icp interface can safely ? borrow ? the icp_scl (p4.4) and icp_sda (p4.5) pins. in most applications, external resistors are required to isolate icp interface traffic from the user application. a typi cal isolation configuration is shown in figure 30 ? 4 . it is strongly recommended to build the icp interface circuit on target system. it will reserve the whole capability for software programming and device options configured. after power - on, the p4.4 and p4.5 of mg82fg5bxx are configured to ocd_scl/ocd_sda for in - system on - chip - debugging function. this is possible because ocd communication is typically performed when the cpu is in the halt state, where the user so ftware is stalled. in this halted state, the ocd interface can safely ? use ? the ocd_scl ( p4.4 ) and ocd_sda (p 4 . 5 ) pins. as mentioned icp interface isolation in figure 30 ? 4 , external resistors are required to isolat e ocd interface traffic from the user application. if user gives up the ocd function, software can configure the ocd_scl and ocd_sda to port pins: p4.4 and p4. 5 by clearing ocde on bit 0 of d con 0 . when user would like to regain the ocd function , user can predict an event that trigger s the software to switch the p4.4 and p4.5 back to ocd_scl and ocd_sda by setting oced as ? 1 ? . or ? erase ? the on - chip flash by icp which clean s the user software to stop the port pins switching . figure 30? 4 . icp and ocd interface circuit ocd _ scl mcu rst ocd _ sda reset input input 1 output 1 input 2 output 2 ocd ice adaptor or megawin writer 4 . 7 k ? 4 . 7 k ? 4 . 7 k ? target system
megawin mg82fg5b xx data sheet 253 30.5. in - chip - programming function the icp, like the traditional parallel programming method, can be used to program anywhere in the mcu, including the flash and mcu?s hardware option. and, owi ng to its dedicated serial programming interface (via the on - chip debug path), the icp can update the mcu without removing the mcu chip from the actual end product, just like the isp does. t he proprietary 6 - pin ?megawin 8051 ic e adapter ? can support the i n - circuit programming of mg82fg5bxx . ?megawin 8051 ic e adapter ? has the in - system storage to store the user program code and device options. so, the tools can perform a portable and stand - alone programming without a host on - line, such as connecting the too l to pc. following lists the features of the icp function: features ? no need to have a loader program pre - programmed in the target mcu. ? dedicated serial interface; no port pin is occupied. ? the target mcu needn ? t be in running state; it just needs to be pow ered. ? capable of portable and stand - alone working without host ? s intervention. the above valuable features make the icp function very friendly to the user. particularly, it is capable of stand - alone working after the programming data is downloaded. this i s especially useful in the field without a pc. the system diagram s of the icp function for the stand - alone programming are shown in figure 30 ? 5 . only five pins are used for the icp interface: the sda line and scl l ine function as serial data and serial clock, respectively, to transmit the programming data from the 6 - pin ?megawin 8051 ic e adapter ? to the target mcu; the rst line to halt the mcu, and the vcc & gnd are the power supply entry of the 6 - pin ?megawin 8051 ic e adapter ? for portable programming application. the usb connector can be directly plugged into the pc?s usb port to download the programming data from pc to the 6 - pin ?megawin 8051 ic e adapter ?. figure 30? 5 . stand - alone programming via icp " megawin 8051 ocd ice" target system icp & ocd interface mcu (less than 20cm) megawin make you win 8051 ice adapter p3.0 scl vcc sda gnd rst usb ocd_scl vdd ocd_sda vss rst n.c. scl vcc sda gnd rst program code download path start button: for code programming
254 mg82fg5b xx data sheet megawin 30.6. on - chip - debug function the mg82fg5bxx is equipped with a megawin proprietary on - chip debug (ocd) interface for in - circuit emulator (ice). the ocd interface provides on - chip and in - system non - intrusive debugging without any target resource occupied. several operations necessary for an ice are supported, such as reset, run, stop, step, run to cursor and breakpoint setting. using the ocd technology, megawin provides the ? megawin 8051 ocd ice ? for the user, as show n in figure 30? 6 . the user has no need to prepare any development board during developing, or the socket adapter used in the traditional ice probe. all the thing the user needs to do is to reserve a 6 - pin connector on the system for the dedicated ocd interface : p3.0, rst, vcc, ocd_sda, ocd_scl and gnd as shown in figure 30? 6 . in addition, the most powerful feature is that it can directly connect the user ? s target system to the keil 8051 ide software for debugging, which directly utilizes the keil ide ? s dscope - debugger function. of course, all the advantages are based on your using keil 8051 ide software. note: ? keil ? is the trade mark of ?keil elektronik gmbh and keil softw are, inc.? . features ? megawin proprietary ocd (on - chip - debug) technology ? on - chip & in - system real - time debugging ? 5 - pin dedicated serial interface for ocd, no target resource occupied ? directly linked to the debugger function of the keil 8051 ide software ? us b connection between target and host (pc) ? helpful debug actions: reset, run, stop, step and run to cursor ? programmable breakpoints, up to 4 breakpoints can be inserted simultaneously ? several debug - helpful windows: register/disassembly/watch/memory windows ? source - level (assembly or c - language) debugging capability figure 30? 6 . system diagram for the ice function " megawin 8051 ocd ice " keil 8051 ide pc target system icp & ocd interface mcu (less than 20cm) megawin make you win 8051 ice adapter p3.0 scl vcc sda gnd rst usb ocd_scl vdd ocd_sda vss rst n.c. scl vcc sda gnd rst note: for more detailed information about the ocd ice, please feel free to contact megawin.
megawin mg82fg5b xx data sheet 255 30.7. sample code for unique id read the mg82fg5b xx is equipped an unique id code (128 - bit) for each one. sample code for unique id reader . ;****************************************************************************************** ; demo program for asm ;* ***************************************************************************************** mov ispcr, #80h mov ifmt, #09h mov ifadrh, #00h mov ifadrl, #0f0h read_1byte_unique_id: mov scmd, #046h mov scmd, #0b9h mov a, ifd ; a = unique id 1 byte data inc ifadrl ;repeat read_1byte_unique_id 16 times to get 16 bytes unique id ;============================================================================= ; demo program for c ;================================= ============================================ u nsigned char id[16]; ispcr = 0x80; ifmt = 0x09; ifadrh = 0; ifadrl = 0xf0; for (i=0;i<16;i++) { scmd = 0x46; scmd = 0xb9; id[i]=ifd; ++ifadrl; }
256 mg82fg5b xx data sheet megawin 31. electrical characteristics 31.1. absolute maximum rating parameter rating unit ambient temperature under bias - 40 ~ + 8 5 c storage temperature - 65 ~ + 150 c voltage on any port i/o pin or rst with respect to vss - 0.5 ~ vdd + 0.5 v voltage on vdd with respect to vss - 0.5 ~ +6.0 v maximum total current through vdd and vss 200 ma maximum output current sunk by any port pin 40 ma *note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the oper ation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
megawin mg82fg5b xx data sheet 257 31.2. dc characteristics v dd = 5.0v 10% , vss = 0v, t a = 25 and execute nop for each machine cycle, unless otherwise specified symbol parameter test condition limits unit min typ max input/ o utput characteristics v ih1 input high voltage (all i/o p orts) e xcept p6.0, p6.1 0 .6 v dd v ih2 input high vol tage ( rst , p6.0, p6.1) 0.75 v dd v il 1 input low voltage (all i/o ports) e xcept p6.0, p6.1 0. 15 v dd v il 2 input low voltage (rst, p6.0, p6.1) 0.2 v dd i ih input high leakage current (all i/o ports) v pin = v dd 0 10 ua i il 1 logic 0 input current (p3 in quasi - mode or other input port with on - chip pull - up resistor ) v pin = 0.4v 20 50 ua i il 2 logic 0 input current (all input only or open - drain ports) v pin = 0.4v 0 1 0 ua i h2l logic 1 to 0 input transition current (p3 in quasi - mode or other input port with on - chip pull - up resistor ) v pin =1.8v 330 500 ua i oh1 output high current ( p3 in quasi - mode or other open - drain output port with on - chip pull - up resistor ) v pin =2.4v 150 2 0 0 ua i oh2 output high current ( all push - pull output ports ) v pin =2.4v 12 m a i ol 1 output low current (all i/o ports) v pin =0.4v 12 ma r rst internal reset pull - down resistance 85 kohm power consumption i op2 normal mode operating current sysclk = 24mhz @ ihrco with pll 4.3 ma i op3 sysclk = 12mhz @ ihrco 2.5 ma i op4 sysclk = 12mhz @ ihrco with adc 3.3 ma i op5 sysclk = 24mhz @ xtal 5 ma i op6 sysclk = 12mhz @ xtal 3.2 ma i op7 sysclk = 6mhz @ xtal 2.6 ma i op8 sysclk = 2mhz @ xtal 1.9 ma i ops1 slow mode operating current sysclk = 12mhz/128 @ ihrco 1. 04 ma i ops2 sysclk = 12mhz/128 @ xtal 1.8 ma i idle1 idle mode operating current sysclk = 12mhz @ ihrco 1.3 ma i idle2 sysclk = 12mhz @ xtal 2 ma i idle3 sysclk = 12mhz/128 @ ihrco 0.85 ma i idle4 sysclk = 12mhz/128 @ xtal 1.6 ma i idle5 s ysclk = 32khz @ ilrco, bod1 disabled 1 0 0 u a
258 mg82fg5b xx data sheet megawin i idle6 sysclk = 32khz/128 @ ilrco, bod1 disabled 100 u a i sub1 sub - clock mode operating current sysclk = 32khz @ ilrco, bod1 disabled 170 ua i sub2 sysclk = 32khz/128 @ ilrco, bod1 disabled 100 ua i wa t watch mode operating current wdt = 32khz @ ilrco in pd mode 6 ua i mon1 monitor mode operating current bod1 enabled in pd mode 120 ua i rtc1 rtc mode operating current rtc operating in pd mode , vdd = 5.0v 10.5 ua rtc operating in pd mode , vdd = 3.0v 4.8 i pd 1 power down mode current 4 ua bod0/bod1 characteristics v bod0 bod0 detection level t a = - 40 to + 8 5 w 1.6 (1) 1 . 7 1.85 (1) v v bod10 bod1 detection level for 2.0v t a = - 40 w to + 8 5 w 1.85 (1) 2.0 2.15 (1) v v bod11 bod1 detection level for 2 .4v t a = - 40 w to + 8 5 w 2.25 (1) 2.4 2.55 (1) v v bod12 bod1 detection level for 3.7v t a = - 40 w to + 8 5 w 3.55 (1) 3.7 3.85 (1) v v bod13 bod1 detection level for 4.2v t a = - 40 w to + 8 5 w 4.05 (1) 4.2 4.35 (1) v i bod1 bod1 power consumption t a = + 2 5 , vdd=5.0v 110 ua t a = + 2 5 , vdd=3.3v 95 operating condition v psr power - on slop rate t a = - 40 w to + 8 5 w 0.05 v/ms v por1 power - on reset valid voltage t a = - 40 w to + 8 5 w 0.1 v v op1 xtal operating speed 0 ? 24 mhz t a = - 40 w to + 8 5 w 2.7 5.5 v v op2 xtal operating s peed 0 - 12mhz t a = - 40 w to + 8 5 w 2.0 5.5 v v op4 cpu operating speed 0 - 24mhz t a = - 40 w to + 8 5 w 2.4 5.5 v v op5 cpu operating speed 0 - 12mhz t a = - 40 w to + 8 5 w 2.0 5.5 v (1) data based on characterization results, not tested in production.
megawin mg82fg5b xx data sheet 259 31.3. external clock characteristics v dd = 2. 0 v ~ 5. 5 v , vss = 0v, t a = - 40 to + 8 5 , unless otherwise specified symbol parameter oscillator unit crystal mode ecki mode min. max min. max 1/t clcl oscillator frequency (vdd = 2.7v ~ 5.5v) 0.03 2 2 5 0 25 mhz 1/t clcl oscil lator frequency 0.032 12 0 12 mhz t clcl clock period 41.6 27.7 ns t chcx high time 0.4t 0.6t 0.4t 0.6t t clcl t clcx low time 0.4t 0.6t 0.4t 0.6t t clcl t clch rise time 5 5 ns t chcl fall time 5 5 ns figure 31? 1 . external clock drive waveform 0 . 45 v t chcx t clch vdd - 0 . 5v 0.7vdd 0.2vdd - 0. 1 t clcx t clcl t chcl 31.4. ihrco characteristics parameter test condition limits unit min typ max supply voltage 2. 0 5.5 v ihrco frequency ta = + 2 5 , afs = 0 12 mhz ta = + 2 5 w , afs = 1 1 1.059 mhz ihrco frequency deviation (factory calibrated) ta = + 2 5 - 1.0 +1.0 % ta = - 40 w to + 8 5 w - 2. 5 (1) +2. 5 (1) % ihrco start - up time ta = - 40 w to + 8 5 w 32 (1) us ihrco power consumption ta = + 2 5 w , vdd=5 .0v 600 ua (1) data based on characterization results, not tested in production. 31.5. ilrco characteristics parameter test condition limits unit min typ max supply voltage 2. 0 5.5 v ilrco frequency ta = + 2 5 32 khz ilrco frequency deviation ta = + 2 5 - 20 (1) +20 (1) % ta = - 40 w to + 8 5 w - 40 (1) +40 (1) % (1) data based on characterization results, not tested in production.
260 mg82fg5b xx data sheet megawin 31.6. ckm characteristics parameter test condition limits unit min typ max supply voltage ta = - 40 to + 8 5 w 2. 4 5.5 v c lock input range ta = - 40 w to + 8 5 w 5 (1) 6 6.5 (1) mhz ckm start - up time ta = - 40 w to + 8 5 w 30 ( 2 ) 100 ( 2 ) us ckm power consumption ta = + 2 5 w , vdd=5.0v 400 ua (1) data guaranteed by design, not tested in production. (2) data based on characterization resu lts, not tested in production. 31.7. flash characteristics parameter test condition limits unit min typ max supply voltage ta = - 40 to + 8 5 w 2. 0 5.5 v flash write (erase/program) voltage ta = - 40 w to + 8 5 w 2.2 5.5 v flash erase/program cycle ta = - 40 w to + 8 5 w 2 0,000 times flash data retention ta = + 2 5 w 100 year
megawin mg82fg5b xx data sheet 261 31.8. adc characteristics vdd= 5 . 0 v, vref + = 5 . 0, vref+ <= vdd , t a = - 40 ~ +85 unless otherwise specified parameter test condition limits unit min typ max supply range supply voltage 2 .4 5.5 v dc accuracy resolution 10 bits integral nonlinearity 1 2 3 lsb differential nonlinearity 1 1.5 2 lsb offset error 2 4 6 lsb conversion rate sar conversion clock 6 mhz conversion time in sar clocks 30 clocks throughput rate 2 0 0 ksps analog inputs adc input voltage range 0 vref+ /vdd v input capacitance 2 pf power consumption power supply current operating mode, 200 ksps 0.6 0.8 1 ma
262 mg82fg5b xx data sheet megawin 31.9. serial port timing characteristics v dd = 5.0v 10% , vss = 0v, t a = - 40 to +8 5 , unless otherwise specified symbol parameter urm0x 3 = 0 urm0x 3 = 1 unit min. max min. max t xlxl serial port clock cycle time 12t 4 t t sysclk t qvxh output data setup to clock rising edge 10t - 20 t - 20 ns t xhqx output data hold after clock rising edge t - 10 t - 10 ns t xhdx input data hold after clock rising edge 0 0 ns t xhdv clock rising edge to input data valid 10t - 20 2t - 20 ns figure 31? 2 . shift register mode timing waveform valid valid valid valid valid valid valid valid 1 2 3 4 5 6 7 0 t xhqx set ri set ti write to sbuf output data clear ri input data clock t xhdx t xlxl t qvxh t xhdv
megawin mg82fg5b xx data sheet 263 31.10. spi timing characteristics v dd = 5.0v 10% , vss = 0v, t a = - 40 to + 8 5 , unless otherwise specified symbol parameter min max units master mode timing t mckh s pi c l k high time 2t t sysclk t mckl s pi c l k low time 2t t sysclk t mis miso valid to s pi c l k shift edge 2t+20 ns t mih spi c l k shift edge to miso change 0 ns t m oh s pi c l k shift edge to mosi change 10 ns slave mode timing t se n ss falling to first s pi c l k edge 2t t sysclk t sd last s pi c l k edge to n ss rising 2t t sysclk t sez n ss falling to miso valid 4t t sysclk t sdz n ss rising to miso high -z 4t t sysclk t ckh s p i c l k high time 4t t sysclk t ckl s pi c l k low time 4t t sysclk t sis mosi valid to s pi c l k sample edge 2t t sysclk t sih s pi c l k sample edge to mosi change 2t t sysclk t soh spi c l k shift edge to miso change 4t t sysclk t slh last s pi c l k edge to miso change (cp ha = 1 only) 1t 2t t sysclk figure 31? 3 . spi master transfer waveform with cpha=0 spiclk ( cpol = 0 ) spiclk(cpol=1) clock cycle 1 2 3 4 5 6 7 8 mosi miso t ckh t ckl t mis t mih t moh figure 31? 4 . spi master transfer waveform with cpha=1 1 2 3 4 5 6 7 8 spiclk(cpol=0) spiclk(cpol=1) clock cycle mosi miso t ckh t ckl t mis t mih t moh
264 mg82fg5b xx data sheet megawin figure 31? 5 . spi slave transfer waveform with cpha=0 spiclk ( cpol=0) spiclk(cpol =1) clock cycle 1 2 3 4 5 6 7 8 mosi miso nss t se t ckh t sd t ckl t sdz t sez t sis t sih t soh figure 31? 6 . spi slave transfer waveform with cpha=1 1 2 3 4 5 6 7 8 t sd t sdz t slh spiclk(cpol=0) spiclk(cpol=1) clock cycle mosi miso nss t se t ckh t ckl t sis t sih t sez t soh
megawin mg82fg5b xx data sheet 265 32. instruction set table 32 ? 1 . instruction set mnemonic description byte execution cycles data trasfer mov a,rn move register to acc 1 1 mov a,direct move direct byte o acc 2 2 mov a,@ri move indirect ram to acc 1 2 mov a,#data move immediate data to acc 2 2 mov rn,a move acc to register 1 2 mov rn,direct move direct byte to register 2 4 mov rn,#data move immediate data to register 2 2 mov direct,a move acc to direct byte 2 3 mov direct,rn move register to direct byte 2 3 mov direct,direct move direct byte to direct byte 3 4 mov direct,@ri move indirect ram to direct byte 2 4 mov direct,#data move immediate data to direct byte 3 3 mov @ri,a move acc to indirect ram 1 3 mov @ri,direct move direct byte to indirect ram 2 3 mov @ri,#data move immediat e data to indirect ram 2 3 mov dptr,#data16 load dptr with a 16 - bit constant 3 3 movc a,@a+dptr move code byte relative to dptr to acc 1 4 movc a,@a+pc move code byte relative to pc to acc 1 4 movx a,@ri move on - chip auxiliary ram(8 - bit address) to acc 1 not support movx a,@dptr move on - chip auxiliary ram(16- bit address) to acc 1 not support movx @ri,a move acc to on - chip auxiliary ram(8 - bit address) 1 not support movx @dptr,a move acc to on - chip auxiliary ram(16 - bit address) 1 not support movx a,@r i move external ram(8 - bit address) to acc 1 not support movx a,@dptr move external ram(16 - bit address) to acc 1 not support movx @ri,a move acc to external ram(8 - bit address) 1 not support movx @dptr,a move acc to external ram(16 - bit address) 1 not supp ort push direct push direct byte onto stack 2 4 pop direct pop direct byte from stack 2 3 xch a,rn exchange register with acc 1 3 xch a,direct exchange direct byte with acc 2 4 xch a,@ri exchange indirect ram with acc 1 4 xchd a,@ri exchange low - orde r digit indirect ram with acc 1 4 arithematic operations add a,rn add register to acc 1 2 add a,direct add direct byte to acc 2 3 add a,@ri add indirect ram to acc 1 3 add a,#data add immediate data to acc 2 2 addc a,rn add register to acc with carry 1 2 addc a,direct add direct byte to acc with carry 2 3 addc a,@ri add indirect ram to acc with carry 1 3 addc a,#data add immediate data to acc with carry 2 2 subb a,rn subtract register from acc with borrow 1 2 subb a,direct subtract direct byte fr om acc with borrow 2 3 subb a,@ri subtract indirect ram from acc with borrow 1 3
266 mg82fg5b xx data sheet megawin subb a,#data subtract immediate data from acc with borrow 2 2 inc a increment acc 1 2 inc rn increment register 1 3 inc direct increment direct byte 2 4 inc @ri incremen t indirect ram 1 4 dec a decrement acc 1 2 dec rn decrement register 1 3 dec direct decrement direct byte 2 4 dec @ri decrement indirect ram 1 4 inc dptr increment dptr 1 1 mul ab multiply a and b 1 4 div ab divide a by b 1 5 da a decimal adjust ac c 1 4 logic operation anl a,rn and register to acc 1 2 anl a,direct and direct byte to acc 2 3 anl a,@ri and indirect ram to acc 1 3 anl a,#data and immediate data to acc 2 2 anl direct,a and acc to direct byte 2 4 anl direct,#data and immediate dat a to direct byte 3 4 orl a,rn or register to acc 1 2 orl a,direct or direct byte to acc 2 3 orl a,@ri or indirect ram to acc 1 3 orl a,#data or immediate data to acc 2 2 orl direct,a or acc to direct byte 2 4 orl direct,#data or immediate data to dir ect byte 3 4 xrl a,rn exclusive - or register to acc 1 2 xrl a,direct exclusive - or direct byte to acc 2 3 xrl a,@ri exclusive - or indirect ram to acc 1 3 xrl a,#data exclusive - or immediate data to acc 2 2 xrl direct,a exclusive - or acc to direct byte 2 4 xrl direct,#data exclusive - or immediate data to direct byte 3 4 clr a clear acc 1 1 cpl a complement acc 1 2 rl a rotate acc left 1 1 rlc a rotate acc left through the carry 1 1 rr a rotate acc right 1 1 rrc a rotate acc right through the carry 1 1 swap a swap nibbles within the acc 1 1 boolean variable manipulation clr c clear carry 1 1 clr bit clear direct bit 2 4 setb c set carry 1 1 setb bit set direct bit 2 4 cpl c complement carry 1 1 cpl bit complement direct bit 2 4 anl c,bit and dir ect bit to carry 2 3 anl c,/bit and complement of direct bit to carry 2 3 orl c,bit or direct bit to carry 2 3 orl c,/bit or complement of direct bit to carry 2 3
megawin mg82fg5b xx data sheet 267 mov c,bit move direct bit to carry 2 3 mov bit,c move carry to direct bit 2 4 boolean v ariable manipulation jc rel jump if carry is set 2 3 jnc rel jump if carry not set 2 3 jb bit,rel jump if direct bit is set 3 4 jnb bit,rel jump if direct bit not set 3 4 jbc bit,rel jump if direct bit is set and then clear bit 3 5 proagram braching acall addr11 absolute subroutine call 2 6 lcall addr16 long subroutine call 3 6 ret return from subroutine 1 4 reti return from interrupt subroutine 1 4 ajmp addr11 absolute jump 2 3 ljmp addr16 long jump 3 4 sjmp rel short jump 2 3 jmp @a+dptr jum p indirect relative to dptr 1 3 jz rel jump if acc is zero 2 3 jnz rel jump if acc not zero 2 3 cjne a,direct,rel compare direct byte to acc and jump if not equal 3 5 cjne a,#data,rel compare immediate data to acc and jump if not equal 3 4 cjne rn,#d ata,rel compare immediate data to register and jump if not equal 3 4 cjne @ri,#data,rel compare immediate data to indirect ram and jump if not equal 3 5 djnz rn,rel decrement register and jump if not equal 2 4 djnz direct,rel decrement direct byte and j ump if not equal 3 5 nop no operation 1 1
268 mg82fg5b xx data sheet megawin 33. package dimension 33.1. lqfp - 32 (7mm x 7mm) figure 33? 1 . lqfp - 32 (7mm x 7mm )
megawin mg82fg5b xx data sheet 269 33.2. sop - 28 figure 33? 2 . sop28
270 mg82fg5b xx data sheet megawin 33.3. sop - 20 figure 33? 3 . s op20
megawin mg82fg5b xx data sheet 271 33.4. s sop - 16 figure 33? 3 . s s op16
272 mg82fg5b xx data sheet megawin 34. revision history table 34 ? 1 . revision history rev descriptions date v 0 .54 1. preliminary version release. 2013/0 7 / 29 v 0 .5 5 1. added fe ature unique - id & unique - id read sample code . 2. modify iap space defined . 2013/10/07 v 0 .5 6 1. added sample code 2. update some of dc characteristics data 2013/10/ 2 1 v 0 .5 8 1. modify chinese note for sample code 2. modify figure 25 - 1 . mg82fg5b32 flash memory configur ation 3. update package dimension data 4. kbi port kbmask: x= 1, 2 or 3 2013/1 1 / 01 v 0 .5 9 1. remove sop - 28 package 2. added adc of dc characteristics data. 2013/11/27 v 0 . 60 1. modify error ocde on bit 0 of pcon3 as d con 0 ( page 243) . 2. added adc voltage reference select ion control 2014/02/ 24 v 0 . 61 added enhance pwm mode description 2014/03/31 v 0 . 6 2 added sop - 28, sop20 , sop16 package 201 5 /0 1 / 2 1 v1.00 added paoe description 2015/04/28 v 1 .01 1. modify the sop16 package format 2. modify twsi sample code 3. rename twsi and twi2 to twi0 and stwi 4. correct dcon0 reset value 2015/06/01 v1.02 modify the contents of s1cfg 2015/09/25 v1.03 1. added ssop16 package and remove sop16 package 2. added section of ordering information 3. modify isp/iap sample code 2015/11/13
megawin mg82fg5b xx data sheet 273 disclaimers herein , megawin stands for ? megawin technology co., ltd. ? life support ? this product is not designed for use in medical, life - saving or life - sustaining applications, or systems where malfunction of this product can reasonably be expected to result in personal injury. customers using or selling this product for use in such applications do so at their own risk and agree to fully indemnify megawin for any damages resulting from such improper use or sale. right to make changes ? megawin reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in mass production, relevant changes will be communicated via an engineering ch ange notification (ecn).

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